CMOS LOGIC

• A circuit that uses complimentary pairs of P channel and N channel

MOFETs is called CMOS.
• CMOS logic ICs combine MOSFETs in various ways to implement logic
functions.
• In CMOS logic gates,a collection of N –type MOSFET is arranged in a
pull down network between the output and low voltage power supply
rails(Vss or quite often ground).
• CMOS logic gates have a collection of P-type MOSFETs in a pull up
network between output and higher level voltage rail(VDD)
• If both P type and N type transistor have their gates connected to the
same input ,p-type MOSFET will be ON when the n type MOSFET is
OFF,and vice –versa.
• The networks are arranged such that one is ON and the other is OFF
for any input pattern.
CMOS inverter.
• The simplified view of CMOS inverter consist of two complementary
non ideal switches as shown in fig.
• The transistor is nothing,but a switch with an infinite off
resistance(for |VGS|<|VT| and a finite ON resistance for |VGS|>|VT|.
Case 1:When Vin is high and equal to VDD
• the NMOS transistor is ON and PMOS transistor is OFF (fig 2 a)
• A direct paths exist between Vout and ground,resulting in Vout=0V.
Case 2:when Vin=0V
• NMOS and PMOS transistors are OFF and ON respectively(fig 2 b).
• Then Vout=VDD
Thus the circuit function as an inverter.
• Advantages of CMOS inverter over other inverter configurations
1)Steady state power dissipation of CMOS inverter circuit is negligible.
2)The voltage transfer characteristics(VTC) exhibits a full output voltage
swing between 0V and VDD.
This results in high noise margin .Also the VTC transition is usually very
sharp and hence ,the CMOS inverter resembles an ideal inverter
characteristics.
Static or DC analysis of CMOS inverter
• A dc analysis determines Vout for a given value of Vin.
• In this type of calculation, it is assumed that Vin is changed slowly,and
that Vout is allowed to stabilize before a measurement is made.
• A DC analysis provides direct mapping of the input to output.
• The DC characteristics is portrayed in Voltage Transfer Curve(VTC)
which is a plot of Vout as a function of Vin.
• This is obtained by varying Vin from 0 to VDD,and finding Vout.
• The end point values are easily obtained with the help of circuits in fig
2.b and 2.c
• If Vin =0V ,Mn is off while Mp is ON.
So Vout =VDD
This defines the output high voltage of the circuit VOH=VDD
That is the highest output voltage is the value of power supply,VDD.
• If Vin=VDD,this turns on Mn while Mp is in cut off as in fig.
The output node is connected to the ground through Mn, defining the
low output voltage
VOL=0V
• The logic swing at the outpu is VL=VOH-VOL=VDD
• This is equal to the full value of the power supply,called full rail
output.
Voltage transfer curve
• Obtained by starting with an input voltage of Vin-0V and then
increasing upto Vin=VDD.
• VGSn=Vin
• VSGp=VS-VG of PMOS
• =VDD-Vin
• Mn is in cut of so long as Vin≤Vtn .
• Since the output voltage is high Vout=VDD,any input voltage in the
range labelled as”0” can be interpreted as a logic 0 input.
• Increasing Vin causes a downward transition in VTC.
• Because the input voltage turns the nFET ON,while the pFET is still
conducting .
• The increase in Vin decreases VSGp,so the pFET becomes a less
efficient conductor and the output falls ,Mp goes into cut off when
• Vin=VDD-|VTP|
• For Vin greater than this voltage ,Vout =0V,since only the nFET is
active. This shows that there is a range of input voltages that act as
logic 1 input values indicated by “1” in the VTC.
• The logic 1 and logic 0 voltage ranges are defined by the changing
slopes of the VTC .
• Point “a” in the curve is where slope has a value of -1 and defines the
input voltage VIL.
• A logic 0 input voltage is defined by
0≤ 𝑽𝑰𝑵 ≤VIL
• The second -1 slope point is labelled as “b” defines the input high
voltage VIH.
• A logic 1 input is defined by
VIH≤ 𝑽𝑰𝑵 ≤VDD
• The voltage noise margins are
• VNMH=VOH-VIH
• VNML=VIL-VOL
Midpoint voltage/switching threshold voltage
• It is defined as the point where the VTC intersects the unity gain line
that is defined by VOUT=VIN =VM
• A value of VIN =VM is in the transition region and doesn’t represent a
Boolean quantity .
For Vin<VM:input voltage is towards logic 0
For Vin> VM:input voltage towards logic 1
Knowing the value of VM thus tell the centre point for input transitions
Calculation of VM (switching threshold voltage)
• To find the midpoint Vin=Vout=VM,equate drain currents
IDn=IDp
But we need to find the operating region (saturation or non
saturation)of each FET.
• Consider the first nFET,the saturation voltage is given by
Vsat=VGSn-VTn
=VM-VTn (VIN =VM=VGSn )
• The drain source voltage is
• VDSn=Vout=VM
• Since VTn is positive number,VDSn>Vsat=VM-VTn
it says that Mn must be saturated
The same arguments can be applied to the pFET(Mp) and Mp is also in
saturation.
Inverter switching characteristics or transient analysis
• Vin(t) has step like characteristics and makes an abrupt transition
from o to 1 at time t1 and back down to 0 at time t2.
• The output reacts to the input,but the output voltage cannot change
instantaneously.
• The output 1 to 0 transition introduces a fall time delay of tf ,while 0
to 1 transition introduce a delay called rise time tr.
• The rise and fall time delay are due to parasitic resistance and
capacitance of the transistors.
• In a logic chain every logic gate must drive another gates.
• The no.of gates is specified by the fan out of the circuit.
• The fan out gate acts as the load to the driving circuit because of their
input capacitance Cin .

• The input capacitance of the inverter is :Cin =CGp+CGn

• The input capacitance to each gate acts as an external load
capacitance ,CL
• CL=3 Cin (from fig 4.b)
• A CMOS NOT gate is used to drive an external load capacitance CL(fig
4.c)
• the complete switching model is shown in fig 4.d
• Where the total ouput capacitance
• Cout=CFET +CL
• Where CFET =CDn+CDp
Fall time calculation
Case 1:Vin changes from 0 to VDD at time t=0
The initial condition Vout(0)=VDD
When the input is switched to VDD,nFET turns on,pFEt is driven to cut
off.
The capacitor Cout is initially charged to VDD and is allowed to
discharge to 0V through nFET resistance Rn
The current leaving the capacitor is
𝑑𝑉𝑜𝑢𝑡 𝑉𝑜𝑢𝑡
i= - Cout = which is a differential equation.
𝑑𝑡 𝑅𝑛
• The output fall time in a generic digital logic gate is called the outpu
high to low time tHL
• tHL=tf=2.2𝜏𝑛
Rise time calculation
Case 2:Vin changes from VDD to 0 V
• This turns on pFET while nFET falls into cut off region.
• The rise time time is identical to the output low to high time tLH
• tLH=tr= 2.2𝜏𝑝

• Fall time and rise time has similar forms because of the symmetry of
the charge and discharge circuits.
1 1
• Maximum signal frequency ,fmax= =
𝑡𝐻𝐿+𝑡𝐿𝐻 𝑡𝑓+𝑡𝑟
• This is the largest frequency that can be applied to the gate.If the
signal frequency exceeds fmax,the output voltage of the gate will not
have sufficient time to stabilize to the correct value.
Power dissipation
• VDD
• IDD

CMOS CIRCUIT

• The current IDD flowing from the power supply to ground gives a
dissipated power of P=VDD .IDD
• Since VDD is constant,we can find P by studying the nature of the
current flow .
• P=PDC+Pdyn
• PDc is the Dc power and Pdyn is the dynamic or switching power.
• Dc power(PDC)
• The dc contribution can be calculated from the voltage transfer curve.
• When Vin is stable at logic 0 value,nFET is off,there is no current flow
path between VDD and ground.
• i.e DC current IDD=0,but in a realistic circuit ,a small leakage current
exist denoted as IDDQ called quiescent leakage current.
• When Vin is switched the current flow reaches peak value at VM
• When the input reaches a logic 1 voltage ,then the pFET Mp turns
off,once again preventing a direct current flow path,but still exust a
leakage current.
• If we assume that the inputs are in stable 0 or 1 states as in idle
system,the DC power dissipation is
• PDC=VDD.IDDQ
• The leakage current IDDQ usually quite small, with typical value of pico
ampere per gate.
Dynamic power dissipation
Use a square wave input voltage Vin(t) as shown with a period T(f=1/T)
• During the first half cycle,Vin=0V
• The current iDD flows through Mp and charges Cout to a voltage of
Vout=VDD
• During the second half cycle,Vin=VDD,turning on nFET Mn.this causes
discharge event where vout decays to 0V.
• The dynamic power Pdyn arises from the observation that a complete
cycle effectively creates a path for current to flow from power supply
to ground.
• During the charge event current flows to the capacitor Cout while the
discharge path to ground completes the circuit.
• Realization of logic functions using CMOS logic
D
• NMOS logic circuits
• In the N channel MOS family,current conduction is because of
electrons.
• The negatively charged electrons are fast moving than holes,which is
positively charged.So the speed of operation of NMOS is faster than
PMOS.
 NMOS basic logic gates
1)NMOS inverter
• Has two NMOS devices,Q1 and Q2.
• Q1 acts as the load MOSFET,Q2 acts as a switching MOSFET.
• Since the gate is always connected to the supply +VDD,the MOSFET Q1
is always ON.So the internal resistance of Q1 acts as the load
resistance RL.
• Compared to both MOSFETs,Q1 is designed have more resistance than
Q2.
• When Vin=0 V,Q2 is OFF,so Vo=VDD
• When Vin=VDD (High voltage),Q2 is ON, so Vo=0 V
2.NMOS NAND gate
Consists of 3 NMOS,Q1 acts as load resistance,Q2 and Q3 acts as
switching MOSFETs.
• Case 1:A=B=0
Q2 and Q3 off,so Vo=VDD
• Case 2:A=0,B=1
Q2=off,Q3 =ON,So Vo=VDD
• Case 3:A=1,B=0
Q2 =ON,Q3=OFF,so Vo=VDD
• Case 4:A=B=1
Q2 and Q3 are ON,so Vo=0V
NMOS NOR gate
• Consists of 3 NMOS transistors Q1,Q2,Q3
• Q1 acts as load resistance,Q2 and Q3 acts as switching MOSFETs.
• Case 1:A=B=0
Q2 and Q3 off,so Vo=VDD
• Case 2:A=0,B=1
Q2=off,Q3 =ON,So Vo=0V
• Case 3:A=1,B=0
Q2 =ON,Q3=OFF,so Vo=0V
• Case 4:A=B=1
Q2 and Q3 are ON,so Vo=0V
Pass transistors
• They are single FETs that passes the signal between drain and source
terminals instead of a fixed power supply value.
• They require less area and wiring,but cannot pass the entire voltage
range.
• NMOS pass transistors are preferred more than PMOS pass transistor
since large electron mobility implies faster switching in NMOS pass
transistor of the same size.
NMOS pass transistor
• As in figure switch is controlled by the gate voltage VG .
• If VG=0,then the transistor is OFF and there is no connection between
input and output.
• If VG=VDD(high voltage),NMOS becomes active and current flows.
Case 1:Logic 1 transfer
• Logic 1 means Vin=VDD
• Assume an initial condition of Vout(t=0)=0V
𝑡
2𝜏𝑛
Vout(t)=Vmax 𝑡
1+
2𝜏𝑛
Where Vmax=VDD-VTn →the maximum voltage transferred through an NMOS
• t→∞Lt Vout(t)=Vmax
• This clearly exhibits the threshold drop problem
• Time constant 𝜏𝑛 = 𝑅𝑛𝐶𝑜𝑢𝑡
• The rise time needed for the output voltage to reach 0.9 Vmax is
tr=18 𝟐𝝉𝒏
• logic 1 transfer event is slow and suffers from threshold loss.
Case 2:Logic 0 transfer
• A logic 0 transfer is analysed by placing Vin =0V.With the initial
condition Vout(t)=Vmax,
2𝑒 −𝑡/𝜏𝑛
• Vout(t)=Vmax Where 𝜏𝑛 = 𝑅𝑛𝐶𝑜𝑢𝑡
1+𝑒 −𝑡/𝜏𝑛
• t→∞Lt Vout(t)= 0
• Which shows that NMOS can pass a logic 0 without any problems.
• The fall time needed for the output to change to 10% of Vmax is
tf=2.94 𝜏𝑛
Comparing rise time and fall time tr≈6tf
So rise time is a limiting factor
PMOS pass transistor
If we use a PFET as a pass transistor,we find the complementary results.
If VG=VDD,the PMOS is OFF and there is no connection between input
and output.
If VG=0,it drives the PMOS active and current flows.
Case 1:logic 1 transfer
• If Vin=VDD,the output charges quite rapidly with a rise time of
• tr=2.94 𝜏𝑝
• Where 𝜏𝑝 = 𝑅𝑝 𝐶𝑜𝑢𝑡
• PMOS is able to transfer a strong logic 1 voltage without any loss
Case 2:Logic 0 transfer
• When a logic 0 is applied at the input ,the output discharges to a level
Vmin=|VTp|
• With a fall time of tf=18 𝜏𝑝
• The discharge is the limiting factor
PMOS pass transistor pass strong ones and NMOS pass transistor pass
strong zeros
Implementation of gates using pass transistor logic
Transmission gates
• These gates are composed of an NMOS transistor and a PMOS
transistor in a parallel arrangement.
• The transmission gate acts as bidirectional switch controlled by the
gate signal S.
• Eventhough the FETs are in parallel,one dominates the conduction
process at any given time.
• The value of the control bit S determines whether the path between
left and right sides(A and B) is open or closed
• When S=0,no path exist,hence no relation between A and B.
• When S=1,transmission gate provides a closed path ,hence B=A.
Transmission gates are superior to pass transistor in two ways:
1)They output both strong 1s and strong 0s
2)The transmission gates consists of two transistors in parallel,this
reduces the resistance value to only half the value of single pass
transistor.
Disadvantages of transmission gate
1)They require more area than NMOS pass circuitry.
2)They require complimented control signal.