EE4271 VLSI Design

Dr. Shiyan Hu Office: EERC 518 shiyan@mtu.edu

The Inverter
Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.

Digital Integrated Circuits2nd

Inverter

Pass-Transistors

Need a circuit element which acts as a switch When the control signal CLK is high, Vout=Vin When the control signal CLK is low, Vout is open circuited We can use NMOS or PMOS to implement it. For PMOS device, the polarity of CLK is reversed.

NMOS based

PMOS based

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Inverter

NMOS Pass Transistors

Initially Vout=0. input=drain, output=source When CLK=0, then Vgs=0. NMOS cut-off When CLK=Vdd, If Vin=Vdd (Vout=0 initially), Vgs>Vt, Vgs-Vt=Vdd-Vt<=Vds=Vdd, NMOS is in saturation region as a transient response and CL is charged. When Vout reaches Vdd-Vt, Vgs=Vdd-(Vdd-Vt)=Vt. NMOS cut-off. However, if Vout drops below Vdd-Vt, NMOS will be turned on again since Vgs>Vt. Thus, NMOS transmits Vdd value but drops it by Vt.

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Inverter

NMOS Pass Transistors - II

If Vin=0 (and CLK=Vdd), source=input, drain=output If Vout=Vdd-Vt (note that it is the maximum value for Vout for the transistor to be on), Vgs=Vdd>Vt, Vds=VddVt=Vgs-Vt The NMOS is on the boundary of linear region and saturation region CL is discharged As Vout approaches 0, the NMOS is linear region. Thus, Vout is completely discharged. When Vout=0, Vds=0 and Ids=0, thus, the discharge is done. NMOS pass transistor transmits a 0 voltage without any degradation

Digital Integrated Circuits2nd

Inverter

PMOS Pass Transistors

Similar to NMOS pass transistor Assume that initially Vout=0 When CLK=Vdd, PMOS cut-off When CLK=0, If Vin=Vdd, PMOS transmits a Vdd value without degradation If Vin=0, PMOS transmits a 0 value with degradation, Vout=|Vt|

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Transmission Gate

An NMOS transmits a 0 value without degradation while transmits a Vdd value with degradation A PMOS transmits a Vdd value without degradation while transmits a 0 value with degradation Use both in parallel, then can transmit both 0 and Vdd well. CLK=0, both transistors cut-off CLK=Vdd, both transistors are on. When Vin=Vdd, NMOS cut-off when Vout=Vdd-Vtn, but PMOS will drag Vout to Vdd. When Vin=0, PMOS cut-off when Vout=|Vtp|, but NMOS will drag Vout to 0.

Digital Integrated Circuits2nd

Inverter

Propagation Delay

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Rising delay and Falling delay

Rising

delay tr=time for the signal to change from 10% to 90% of Vdd Falling delay tf=time for the signal to change from 90% to 10% of Vdd Delay=time from input signal transition (50% Vdd) to output signal transition (50% Vdd).

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Delay

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Inverter

Inverter falling-time

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Inverter

NMOS falling time

VDD
For NMOS

1.

S
2.

Vin=0, Vgsn=0<Vt, Vdsn=Vout=Vdd, NMOS is in cut-off region, X1

Vin=Vdd, instantaneously, Vgsn=Vdd>Vt,Vdsn=Vout=Vdd, VgsnVtn=Vdd-Vtn<Vdd, NMOS is in saturation region, X2 The operating point follows the arrow to the origin. So Vout=0 at X3.

Vin

D
D S

Vout CL
3.

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NMOS falling time

tf1 tf2

When Vin=Vdd, instantaneously, Vgsn=Vdd tf=tf1+tf2 tf1: time for the voltage on CL to switch from 0.9Vdd to VgsnVtn=Vdd-Vtn tf2: time for the voltage on CL to switch from Vdd-Vtn to 0.1Vdd

Digital Integrated Circuits2nd

Inverter

NMOS falling time

For

Vgsn=Vdd Vdsn=Vout

tf1:

Integrate

Vout from 0.9Vdd to Vdd-Vt

For

tf2, we have

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NMOS falling time

tf=tf1+tf2

Assume

Vt=0.2Vdd

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Rising time

Assume

|Vtp|=0.2Vdd

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Falling and Rising time

Assume

Vtn=-Vtp, then we can show

that Thus, for equal rising and falling time, set That is, Wp=2Wn since up=un/2

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Inverter

Power Dissipation

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Inverter

Where Does Power Go in CMOS?

Dynamic Power Consumption
Charging and Discharging Capacitors

Short Circuit Currents

Short Circuit Path between Supply Rails during Switching

Leakage
Leaking diodes and transistors

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Inverter

Dynamic Power Dissipation

Vdd

Vin

Vout

CL

Power = CL * Vdd2 * f

Not a function of transistor sizes Need to reduce CL, Vdd, and f to reduce power.

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Inverter

Dynamic Power

Dynamic power is due to charging/discharging load capacitor CL In charging, CL is loaded with a charge CL Vdd which requires the energy of QVdd= CL Vdd2, and all the energy will be dissipated when discharging is done. Total power = CL Vdd2 If this is performed with frequency f, clearly, total power = CL Vdd2 f

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Dynamic Power- II

If the waveform is not periodic, denote by P the probability of switching for the signal The dynamic power is the most important power source It is quadratically dependant on Vdd It is proportional to the number of switching. We can slow down the clock not on the timing critical path to save power. It is not dependent of the transistor itself but the load of the transistor.

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Inverter

Short Circuit Currents

Vd d

Happens when both transistors are on.

Vin CL Vout

If every switching is instantaneous, then no short circuits.

Longer delay -> larger short circuit power

0.15

IVDD (mA)

0.10

0.05

0.0

1.0

2.0 3.0 Vin (V)

4.0

5.0

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Short-Circuit Currents

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Leakage
Vd d

Vout

Drain Junction Leakage Sub-Threshold Current

Sub-threshold current one of most compelling issues Sub-Threshold Current Dominant Factor in low-energy circuit design.
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Subthreshold Leakage Component

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Principles for Power Reduction

Prime

choice: Reduce voltage

Recent years have seen an acceleration in supply voltage reduction Design at very low voltages still open question (0.5V)
Reduce

switching activity Reduce physical capacitance

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Inverter

Impact of Technology Scaling

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Goals of Technology Scaling

Make

things cheaper:

Want to sell more functions (transistors) per chip for the same money Build same products cheaper, sell the same part for less money Price of a transistor has to be reduced
But

also want to be faster, smaller, lower power

Inverter

Digital Integrated Circuits2nd

Scaling
Goals

of scaling the dimensions by

30%:
Reduce gate delay by 30% Double transistor density
Die

size used to increase by 14% per generation Technology generation spans 2-3 years
Inverter

Digital Integrated Circuits2nd

Technology Scaling

Devices scale to smaller dimensions with advancing technology. A scaling factor S describes the ratio of dimension between the old technology and the new technology. In practice, S=1.2-1.5.

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Inverter

Technology Scaling - II

In practice, it is not feasible to scale voltage since different ICs in the system may have different Vdd. This may require extremely complex additional circuits. We can only allow very few different levels of Vdd. In technology scaling, we often have fixed voltage scaling model. W,L,tox scales down by 1/S Vdd, Vt unchanged Area scales down by 1/S2 Cox scales up by S due to tox Gate capacitance = CoxWL scales down by 1/S scales up by S Linear and saturation region current scales up by S Current density scales up by S3 P=Vdd*I, power density scales up by S3 Power consumption is a major design issue

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Summary

Inverter
Five regions

Transmission gate Inverter delay Power

Dynamic Leakage Short-circuit

Technology scaling

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Inverter