University of Gondar Institute of Technology

IoT
Very Large Scale Integrated (VLSI ) Design
(CoEng4094)

Lecture 02 B: CMOS Inverter

By Beyene Jember
 Objectives
 Understand static CMOS inverter
 How NMOS and PMOS function as switches
 Why NMOS switch is tied to ground (pull down signal) and PMOS switch is tied
to VDD (pull up signal).
 Illustrate CMOS inverter logic circuit using NMOS and PMOS transistor
 Operation of CMOS inverter
 Characteristics of CMOS inverter operation
 CMOS inverter voltage transfer characteristic (VTC).
 Noise Margin
 Propagation delay
 Power dissipation
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 Review: The MOS Transistor
 Disadvantage
 Weak LOW output
 VOL= VDDRN/(RN+RD)
 Unsuitable for VLSI fabrication
 Large chip area
 Asymmetric switching characteristics
 Charging time will be greater than discharging time
 Large static power dissipation

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 Complementary Circuit
 Modeling inverter using the double switch model.
 The basic assumption is that the switches are Complementary,
 i.e. when one is ON, the other is OFF.
 When the top switch is ON, the supply voltage propagates to
the output node.
 When the bottom switch is ON, the ground voltage is
propagated out.

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 CMOS Operation
 IDN = -IDP
 VGSN = Vin
 VSGP = VDD – Vin =>VGSP=Vin-VDD
→Vin=VGSP+VDD
 VDSN = Vout
 VSDP=VDD –Vout => VDSP=Vout-VDD

⁃ Vout=VDSP+VDD

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 CMOS Inverter: Analysis

No power consumption while idle in any logic state!

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 CMOS Inverter…

A Y

0 1

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CMOS Inverter…

A Y

0 1

1 0

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 CMOS Inverter…
 In CMOS, we use two transistors PMOS ( as PUN) and NMOS (as PDN).
 PULL UP is something that pulls the output up from ground or “output has been pulled
up to source voltage"
 PULL DOWN is that pulls the output down to ground or “output is pulled down to
ground"
 In CMOS, when the input is high, NMOS gets ON and pulls down the output to
ground(i.e., output becomes LOW).
 Whereas, when the input voltage is low, PMOS gets ON and pulls the output up from the
ground (i.e., output becomes HIGH).
 So we call PMOS as PULL UP transistor and NMOS as PULL DOWN transistor.

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 Why PMOS as PUN?

With the output load initially at GND. VT drop cannot pass full VDD

 PMOS can pass VDD without VT drop : Good for pass logic “ 1” or “HIGH”
 A PMOS switch succeeds in charging the output all the way to VDD
 NMOS device fails to raise the output above VDD-VTn.
 Once the output reaches VDD-VTn. the transistor switches off, and the output
capacitance stops charging.
 PMOS Transistors pass a 1 better than a 0.
 PMOS transistor produce a strong 1 and a weak 0. 10
 Why NMOS as PDN?

The output capacitance is initially charged to VDD

 NMOS can pass GND without VT drop : Good for pass logic “ 0 ”or “ LOW”
 An NMOS device pulls the output all the way down to GND, while a PMOS lowers the
output no further than |VTp|
 The PMOS turns off at that point, and stops contributing discharge current
 NMOS Transistors pass a 0 better than a 1
 NMOS transistor generate a strong 0 and a weak 1.
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 Signal Strength
 Strength of signal
 How close it approximates ideal voltage source

 VDD and GND rails are strongest 1 and 0

 NMOS pass strong 0
 But degraded or weak 1

 PMOS pass strong 1

 But degraded or weak 0

 Thus NMOS are best for pull-down network

 While PMOS are best for pull-up network 12
 Reading Assignment
 Load Line Analysis
 CMOS inverter voltage transfer characteristic (VTC).
 Noise Margin

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 Properties of CMOS
 Full rail-to-rail swing  high noise margins

 Logic levels not dependent upon the relative device sizes  transistors can be minimum size
 ratioless

 Always a path to Vdd or GND in steady state  low output impedance

 large fan-out (albeit with degraded performance)

 Extremely high input resistance (gate of MOS transistor is near perfect insulator)
 nearly zero steady-state input current

 No direct path steady-state between power and ground  no static power dissipation

 Propagation delay function of load capacitance and resistance of transistors 14

CMOS Inverter: Transient Response

(a) Low-to-high
b) High-to-low

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 CMOS Inverter: Transient Response…
 What is the output capacitance?
The output capacitance of a CMOS inverter is simply a value that represents the total
capacitance associated with the inverter output.
 This includes the internal capacitances of the MOSFET devices, the wiring capacitance,
and the capacitance of the device that the output is connected to!

Schematic showing all capacitances associated

with the output of a CMOS inverter.

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 CMOS Inverter: Transient Response…
 Review: RC Circuits

 RC time-constant: dictates how rapidly the output voltage reacts to the voltage rise on input
(step function).
 Larger RC, slower response 17
 CMOS inverter: Propagation delay
 Inverter propagation delay: time delay between input and output signals; figure of merit of
logic speed.

tR  rise time between 10% and 90% of total swing

tF  fall time between 90% and 10% of total swing
tPHL  propagation delay from high-to-low between
50% points
tPHL  propagation delay from low-to-high between
50% points

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 CMOS inverter: Propagation delay…
 Simplifications for hand calculations:
• Consider input waveform is an ideal square wave
• Propagation delay times = delay times to 50% point

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 CMOS inverter: Propagation delay…
 Switch-level model
 Delay estimation using switch-level model (for general RC circuit):

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 CMOS inverter: Propagation delay…
 Switch-level model
 Delay estimation using switch-level model (for general RC circuit):

For fall delay

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 Power and Energy Consumption
 The power consumption of a design determines
 How much energy is consumed per operation
 How much heat the circuit dissipates.

 These factors influence a great number of critical design decisions, such as

 The power supply capacity
 The battery lifetime
 Supply-line sizing
 Packaging and
 Cooling requirements.
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 Power and Energy Consumption…
 Therefore, power dissipation is an important property of a design that affects
 Feasibility

 Cost and

 Reliability.

 In the world of high-performance computing power consumption limit

 Dictated by the chip package and the heat removal system

 Determine the number of circuits that can be integrated onto a single chip

• How fast they are allowed to switch.

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 Power dissipation
 Power dissipation in CMOS circuits comes from two components:
 Static Dissipation
 When input is not switching

▪ Subtreshold conduction
▪ Leakage through reverse biased diodes

 Dynamic Dissipation
 Dynamic capacitive power
 Due to charging and discharging (switching) of load capacitance
 Dynamic short-circuit power
 Direct current from VDD to GND when both transistors are on. 24
Power dissipation…
Instantaneous power dissipation

Energy delivered to capacitor

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 Power dissipation…
Energy delivered to capacitor

Stored energy

Energy dissipation

 If the charge/discharge cycle is repeated f times/second, where f is the clock frequency

Energy dissipated in pull-up plus pull-down

Dynamic power dissipation

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