数字集成电路原理

Inverter

刘佳欣
liujiaxin@uestc.edu.cn
Outline
p Introduction
pThe Staic behavior
p Switching Threshold
p Noise Margins
p Robustness
pThe Dynamic behavior: Performance of Inverter
p Computing the Capacitances
p First-Order Analysis
p Propagation Delay from a Design Perspective
pPower and Energy

2
The CMOS Inverter: A First Glance
N Well VDD

VDD PMOS
2l

Contacts
PMOS
In Out
In Out
Metal 1
Polysilicon
NMOS

NMOS
GND

3
Two Inverters in Series: The Buffer

Share power and ground

Abut cells

VDD
Connect in Metal

4
Switch Model of Inverter
VDD

PMOS V DD V DD
In Out

Rp
NMOS

V out
V out

Rn

V in = V DD V in = 0

5
CMOS Inverter Load Characteristics
VDD

PMOS Combine the VTC of NMOS and PMOS

In Out

NMOS

0 2.5
6
CMOS Inverter VTC

7
Inverter Gain

-2

-4

-6

-8
gain

-10

-12

-14

-16

-18
0 0.5 1 1.5 2 2.5
V (V)
in

8
Dynamic Switch Model of Inverter

Charging Discharging

9
Outline
p Introduction
pThe Staic behavior
p Switching Threshold
p Noise Margins
p Robustness
pThe Dynamic behavior: Performance of Inverter
p Computing the Capacitances
p First-Order Analysis
p Propagation Delay from a Design Perspective
pPower and Energy

10
Switching Threshold

VDD

PMOS
In Out

NMOS

11
Switching Threshold

12
VM vs. r

13
Outline
p Introduction
pThe Staic behavior
p Switching Threshold
p Noise Margins
p Robustness
pThe Dynamic behavior: Performance of Inverter
p Computing the Capacitances
p First-Order Analysis
p Propagation Delay from a Design Perspective
pPower and Energy

14
Mapping Logic Levels to Voltage Domain

15
Determining VIH and VIL

16
Determining g
At VM, both PMOS and NMOS are in saturation region

g is mainly determined by process.

17
Simulated VTC
p Example: Simulated VTC of an inverter in 0.25um CMOS

NML

VIL

VIH

NMH

18
Outline
p Introduction
pThe Staic behavior
p Switching Threshold
p Noise Margins
p Robustness
pThe Dynamic behavior: Performance of Inverter
p Computing the Capacitances
p First-Order Analysis
p Propagation Delay from a Design Perspective
pPower and Energy

19
PVT Variation
p CMOS transistor parameters very with PVT

p Process
Ø Carrier mobility -->kp, kn
Ø Threshold voltage
p (Supply) Voltage
Ø Vgs, Vds
p Temperature
Ø Threshold voltage
Ø Carrier mobility -->kp, kn

20
Robustness – Process Variations
p Impact of process variations on static CMOS inverter VTC

SF

TT

FS

21
Robustness – Supply Voltage Scaling
p Impact of supply voltage on static CMOS inverter VTC

22
Outline
p Introduction
pThe Staic behavior
p Switching Threshold
p Noise Margins
p Robustness
pThe Dynamic behavior: Performance of Inverter
p Computing the Capacitances
p First-Order Analysis
p Propagation Delay from a Design Perspective
pPower and Energy

23
Propagation delay
pDelay of the inverter is determined by the time it takes to
charge and discharge the load capacitor CL

Charging Discharging

24
Inverter Load Capacitance
pThe capacitance at the inverter output node

• Capacitance of the inverter itself: Cg12, Cdb2， Cdb1

• Wire capacitance: Cw
• Capacitance of the fan-out stage: Cg3, Cg4
25
Outline
p Introduction
pThe Staic behavior
p Switching Threshold
p Noise Margins
p Robustness
pThe Dynamic behavior: Performance of Inverter
p Computing the Capacitances
p Delay: First-Order Analysis
p Propagation Delay from a Design Perspective
pPower and Energy

26
Delay Definitions

27
How to Reduce Propagation Delay

28
Example

• Delay reduces with VDD increases

• Insensitive to VDD with high VDD
29
Outline
p Introduction
pThe Staic behavior
p Switching Threshold
p Noise Margins
p Robustness
pThe Dynamic behavior: Performance of Inverter
p Computing the Capacitances
p Delay: First-Order Analysis
p Propagation Delay from a Design Perspective
pPower and Energy

30
PMOS/NMOS Ratio

VDD

3~4×
PMOS
In Out

NMOS
1×

Optimized noise margin and symmetrical

31
PMOS/NMOS Ratio

Ø Reqp /Reqn: resistance PMOS/NMOS with identical size

Ø r = Reqp /Reqn: resistance ratio of identically-sized P- and NMOS transistors (r: 3~4) 32
PMOS/NMOS Ratio

Propagation delay of CMOS inverter as a

function of the PMOS/NMOS transistor ratio β

33
Sizing Inverter for Performance

Ø tp0 is independent of the sizing of the gate

Ø Infinite S leads to minimum delay

34
Device Sizing
p Example: Reducing inverter delay by sizing the NMOS and PMOS
transistor with an identical factor S for a fixed fan-out

Large Req, small Cint

Small Req, large Cint

35
How to drive a large load capacitor
p Question: How to drive a large load capacitor?

36
Inverter Chain
pQuestion: How to drive a large load capacitor?

pUse inverter chain

Ø How to size the inverters for a given number of stage?
Ø How many stages are needed to minimize the delay?

37
Sizing the Inverter Chain

38
Choosing the number of Inverter Chain
p Delay of inverter chain:
f e
 0
N  ln(F )

f  3.6
 1
N  log Ff

39
Choosing the number of Inverter Chain

p Use inverter chain

Ø How to size the inverters for a given number of stage?
ü Size each stage with the same effective fan-out f

Ø How many stages are needed to minimize the delay?

ü Select f ≈ 4, then solve N

40
Example: f?
pExample:
Ø For N=3, F=8, compute the f of each stage

41
Buffer Design
pExample:
Ø For F = 64, compute the tp with different inverter
stages. Assuming γ=1.

42
Outline
p Introduction
pThe Staic behavior
p Switching Threshold
p Noise Margins
p Robustness
pThe Dynamic behavior: Performance of Inverter
p Computing the Capacitances
p Delay: First-Order Analysis
p Propagation Delay from a Design Perspective
pPower and Energy

43
Where Does Power Go in an Inverter?

44
Dynamic Power Dissipation

45
Dynamic Power & Switching Activity

46
Dynamic Power & Switching Activity

47
Short Circuit Currents
ts=tr/0.8

48
Impact of Load Capacitance

p Short circuit current goes to

zero if tf /tr of Vout >> tr /ts of Vin

49
Minimizing Short-Circuit Power

1. Reduce peak current

Ø Make tsout > tsin?
No! Large trs,out cause large
short-circuit current in fan-out stage
Ø Make trs,out = trs,in
2. Reduce short circuit time
Ø Lower VDD
Ø If VDD<VTn + |VTp|, then short-
circuit power can be eliminated

50
Transistor Leakage Current

p Sub-threshold current is one of most compelling issues

in low-energy circuit design!
51
Subthreshold Leakage

JS = 10-100 pA/mm2 at 25 deg C for 0.25mm CMOS

JS doubles for every 9 deg C!

52
Reverse-Biased Diode Leakage
GATE

p+ p+
N

Reverse Leakage Current

+
V
- dd

IDL = JS  A

JS = 1-5pA/mm2 for a 1.2mm CMOS technology

JS = 10-100 pA/mm2 at 25 deg C for 0.25mm CMOS
JS doubles for every
o 9 deg C!
Js double with every 9 C increase in temperature

53
Energy, Power-Delay Product,
Energy-Delay Product

fmax=1/2tp

54
Thank you!