MOS INVERTERS

STATIC CHARACTERISTICS

SACHIN DHARIWAL
Assistant Professor
Subject Code: EC-302 ECE Department, DTU
OBJECTIVE
▪ MOS Inverter

▪ Ideal Inverter

▪ Practical nMOS Inverter

▪ Noise Immunity and Noise Margin

▪ Power and Area Consideration

▪ Resistive Load Inverter

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Ideal Inverter
Inverter: Logic gate: Perform Boolean operation on a single input variable.
Inverter Design: Forms significant bias for digital circuit design.

Positive Logic Convention:

Logic 1→ High voltage VDD
Logic 0 → Low voltage 0 V

Voltage Transfer Characteristics (VTC)

Inverter Threshold Voltage (𝑽𝒕𝒉 ):

𝑉𝐷𝐷 (logic 0)
𝑉𝑡ℎ =
2
(logic 1)

Shape of VTC:
▪ Depends upon the type of inverter VTC of an ideal inverter
▪ Basically decides by the design process
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Practical nMOS INVERTER
Input voltage

Output voltage

No body effect

nMOS transistor is called driver transistor.

Load:
▪ 2 terminal circuit element with current 𝐼𝐿 and voltage 𝑉𝐿 (𝐼𝐿 ).
▪ Decides the characteristics of the inverter circuit.

▪ Output terminal of an inverter is connected to input of another inverter

▪ Shown by a lumped capacitance (𝐶𝑜𝑢𝑡 ).
▪ 𝐼𝐺 = 0 for all practical purpose.

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Practical nMOS INVERTER
Voltage Transfer Characteristics (VTC)
Applying KCL at output node

𝑉𝑜𝑢𝑡 as a function of 𝑉𝑖𝑛 under DC condition can be found out.

For low input voltage, MOS is in cut-off,
output voltage is 𝑉𝑂𝐻 (output high voltage).

As 𝑉𝑖𝑛 ↑, Driver transistor starts conducting and 𝑉𝑜𝑢𝑡 ↓.

Out voltage drops gradually with a finite slope.
Two critical points on the curve where slope becomes -1 i .e. 𝑉𝐼𝐿 and 𝑉𝐼𝐻

As 𝑉𝑖𝑛 ↑ further 𝑉𝑜𝑢𝑡 continues to drop and reaches 𝑉𝑂𝐿 at As 𝑉𝑖𝑛 = 𝑉𝑂𝐻
Threshold Voltage:
Transition voltage defined at point where on VTC.
Five critical points on the VTC curve.
𝑉𝑂𝐻 , 𝑉𝑂𝐿 , 𝑉𝐼𝐿 , 𝑉𝐼𝐻 , 𝑉𝑡ℎ
VTC of practical nMOS inverter
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Practical nMOS Inverter
Voltage Transfer Characteristics (VTC)

VTC of practical nMOS inverter

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Practical nMOS Inverter
Noise Immunity and Noise Margin

Assume Input voltage of 1st inverter is

Output voltage of 1st inverter is a logic “0.”
Input voltage at 2nd inverter <VOL.(Logic 0, Correctly Interpreted)
Input voltage at 2nd inverter >VIL. (Logic 1, Wrongly Interpreted)

Assume 2nd inverter output is VOH (Logic 1)

Input voltage at 3rd inverter >VOL.(Logic 1, Correctly Interpreted)
Input voltage at 2nd inverter <VIH. (Logic 0, Wrongly Interpreted)

Noise Margin:
Signal level tolerances for digital circuits is called noise margins
and denoted by NM.
𝑁𝑀 ↑, 𝑁𝑜𝑖𝑠𝑒 𝐼𝑚𝑚𝑢𝑛𝑖𝑡𝑦 𝑜𝑓 𝑡ℎ𝑒 𝑐𝑖𝑟𝑐𝑢𝑖𝑡 ↑

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Practical nMOS Inverter
Noise Immunity and Noise Margin
Shape of VTC is non-linear i.e.

Uncertain region / Transition region:

▪ Region from VIL to VIH.
▪ Reducing this width is one of the most important design objective.
▪ Slope↑, Transition region width↓, Noise Margin↑.

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Power and Area Consideration
Chip→ contains millions of logic gates
Each gate → Generates heat
▪ Heat removal is essential.
▪ Important to reduce heat dissipation by the circuit in both DC
and dynamic operation.
DC power dissipation of inverter circuit
VDD →supply voltage
IDC → Power drawn from supply in steady state

IDC depends upon input and output voltage levels.

Assume 50% of operation time for logic 1 and logic 0.

▪ MOS transistors Area ↓, Chip Area ↓

▪ Gate Area of MOS= 𝑊 × 𝐿
▪ MOS has minimum area when Gate (Channel) has smaller dimensions
𝑊
also 𝐿 ≈ 1.

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Resistive Load Inverter
Driver device: Enhancement type nMOS
Load: Linear resistor RL
For static behaviour of the circuit, output load capacitance
is not shown.
ID=IR
𝜆=0
VSB=0
VDS=Vout
Resistive load inverter circuit
VGS=Vin
Threshold voltage of driver=VTO
Vin<VTO (Cut-off), Vout=VDD
Vin>VTO, nMOS goes into saturation, (VDS=VDD)>VGS-VTO

As Vin↑, ID ↑, Vout ↓, when Vin>Vout+VTO, nMOS enters in linear mode.

And Vout continues to decrease.

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Resistive Load Inverter
5 critical voltage points decides the steady state behaviour of the inverter.
1. Calculation of 𝑽𝑶𝑯
When the Vin is low, driver transistor is in cut-off

Resistive load inverter circuit

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Resistive Load Inverter
2. Calculation of 𝑽𝑶𝑳
Assume Vin=VOH

Since Vin-VTO>Vout, driver operates in linear region

Using KCL,
Resistive load inverter circuit

choose the one that is physically correct, i.e., the value of the
output low voltage must be between 0 and VDD

KnRL is important parameter. 12

Resistive Load Inverter
3. Calculation of 𝑽𝑰𝑳
▪ VIL →smaller voltage at which the slope of the VTC becomes equal to (-1)
i.e., dVout/dVin, = - 1
▪ when Vin=VIL, the output voltage (Vout) is only slight<VOH
Vout > Vin- VTO, driver transistor operates in saturation.
KCL at output node
………………(A)

Take derivative w.r.t Vin Resistive load inverter circuit

Substitute derivative value=-1 at Vin=VIL

………………(B)

Substitute VIL value in equation (A)

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Resistive Load Inverter
4. Calculation of 𝑽𝑰𝑯
▪ VIH →Larger voltage at which the slope of the VTC becomes equal to (-1)
i.e., dVout/dVin, = - 1
▪ when Vin=VIL, the output voltage (Vout) is only slight>VOL
Vout < Vin- VTO, driver transistor operates in linear region.
KCL at output node

………………(C)
Resistive load inverter circuit
Take derivative w.r.t Vin

Substitute derivative value=-1 at Vin=VIH

………………(D)

Solving eqn A & B, to get the value of Vout

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Resistive Load Inverter
4. Calculation of 𝑽𝑰𝑯
Positive solution of second order equation when Vin=VIH

Substitute Vout in equation D

Resistive load inverter circuit

VDD and VTO are decided by system related constraint.
KnRL→ Design parameter adjusted by the circuit designer

Note:
KnRL↑, VOL↓, shape of VTC approaches ideal inverter with large
Transition slope.

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Resistive Load Inverter
5. Calculation of Vth
Put Vout=Vin=Vth in Equation A, and solve the quadratic
equation for Vth.

Resistive load inverter circuit

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Resistive Load Inverter
Power Consumption and Chip Area
Average DC power consumption is found out by taking two cases.

When Vin=VOL, Driver Transistor is in cut-off condition.

IDC=0
When Vin=VOH, IDS≠ 0

Assuming 50% of operation time for logic 1 and logic 0

PDC (average)=VDD × IDC (average)

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Resistive Load Inverter
Power Consumption and Chip Area
Chip area depends upon two parameters.
𝑊
1. 𝐿 ratio of driver transistor
2. Load resistor RL.
Resistor area depends upon the fabrication technology.

Diffused Resistor:
▪ Isolated n/p type diffusion region with one contact on
each end.
▪ Resistance is decided by the doping density and dimensions of the resistor.
sheet resistance range (20-100 ohm/Sq). Diffused resistor layout
▪ Large area is required to achieve hundreds of k-ohm resistance.
▪ Not practical for VLSI applications.

Undoped Polysilicon Resistor:

▪ Have sheet resistance in the order of 10 M-ohm/Sq.
▪ Resistance value can not be controlled very accurately, due to this there is large
variation in VTC.

Undoped polysilicon resistor layout

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Numerical
Q1:

Soln: For V , driver transistor works in linear region.

OL
VOH=VDD, VOL=0.2

From KCL at output node,

Putting the given values

On solving

Choose RL in hundreds of k-ohm range, and W/L as 1.

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Numerical
Q2:

Soln:

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Numerical
Q2:

Soln:

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THANK YOU

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