CSC15107: Computer

Architecture
Lecture – 17: Pipelined Processor – Exception Handling
10 September 2020
 Pipelined Processor
●
What is Pipelining?
●
Design of MIPS Pipelined Processor
●
Hazards:
– Structural
– Data
– Control
●
Implementation hardness – Exceptions
●
FP operations
What Makes Pipelining Hard?

5 independent axes to characterize exceptions:

• Synchronous versus asynchronous

• User requested versus coerced
• User maskable versus user nonmaskable
• Within versus between instructions
• Resume versus terminate
What Makes Pipelining Hard?
What Makes Pipelining Hard?

How to handle exceptions?

The most difficult exceptions have two properties:
(1) they occur within instructions (that is, in the middle of the
instruction execution corresponding to EX or MEM pipe
stages), and
(2) they must be restartable.

• Force a trap instruction into the pipeline on the next IF.

• Until the trap is taken, turn off all writes for the faulting instruction
and for all instructions that follow in the pipeline
• Save PC of the faulting instruction
 What Makes Pipelining
Hard?
What happens on exception while in delay slot ?
• Next instruction is not sequential
solution: save multiple PCs
• Save current and next PC
• Special return sequence, more complex hardware

Precise Exceptions
 MIPS Exception
Handling
Stage Problem that causes the interrupt
IF Page fault on instruction fetch; misaligned memory
access; memory-protection violation
ID Undefined or illegal opcode
EX Arithmetic interrupt
MEM Page fault on data fetch; misaligned memory
access; memory-protection violation
 What Makes
Pipelining Hard?
LD IF ID EX MEM WB
ADD IF ID EX MEM WB

• Simultaneous exceptions in more than one pipeline stage, e.g.,

– Load with data page fault in MEM stage
– Add with instruction page fault in IF stage
– Add fault will happen BEFORE load fault
• Solution #1
– Interrupt status vector per instruction
– Defer check until last stage, kill state update if exception
• Solution #2
– Interrupt ASAP
– Restart everything that is incomplete
 What Makes
Pipelining Hard?
Here’s what happens on a data page fault.
1 2 3 4 5 6 7 8 9
i IF ID EX MEM WB
i+1 IF ID EX MEM WB <­page fault
i+2 IF ID EX MEM WB <­squash
i+3 IF ID EX MEM WB <­squash
i+4 IF ID EX MEM WB <­squash
i+5 trap ­> IF ID EX MEM WB
i+6 trap handler ­ > IF ID EX MEM WB
 What Makes Complex
Instructions
Pipelining Hard?
Complex Addressing Modes and Instructions
• IA-32 Address modes: Autoincrement causes register change during
instruction execution
– Interrupts? Need to restore register state
– Adds WAR and WAW hazards since writes are no longer the last
stage.

• Memory-Memory Move Instructions

– Must be able to handle multiple page faults
– Long-lived instructions: partial state save on interrupt
 What Makes Complex
Instructions
Pipelining Hard?

VAX: differ radically in the number of clock cycles they

will require
- divide into microinstructions