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CMOS Inverter
Summary of transistor operation
NMOS transistor PMOS transistor
 nMOS transistor

pMOS transistor
The CMOS Inverter
 CMOS Inverter
N Well VDD

VDD PMOS
2λ

Contacts
PMOS
In Out
In Out
Metal 1
Polysilicon
NMOS

NMOS
GND

4: DC and Transient Response CMOS VLSI Design Slide 

 Two Inverters
Share power and ground

Abut cells

VDD
Connect in Metal

4: DC and Transient Response CMOS VLSI Design Slide

 CMOS Inverter as Switch
V DD V DD

tpHL = f(Ron.CL)
Rp
= 0.69 RonCL

V out
V out
CL
CL
Rn

V in 5 0 V in 5 V DD
(a) Low-to-high (b) High-to-low
4: DC and Transient Response CMOS VLSI Design Slide
 DC Response
‰ DC Response: Vout vs. Vin for a gate
‰ Ex: Inverter
– When Vin = 0 -> Vout = VDD
– When Vin = VDD -> Vout = 0
VDD
– In between, Vout depends on
transistor size and current Idsp
Vin Vout
– By KCL, must settle such that Idsn
Idsn = |Idsp|
– We could solve equations
– But graphical solution gives more insight

4: DC and Transient Response CMOS VLSI Design Slide

 Transistor Operation
‰ Current depends on region of transistor behavior
‰ For what Vin and Vout are nMOS and pMOS in
– Cutoff?
– Linear?
– Saturation?

4: DC and Transient Response CMOS VLSI Design Slide

 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vgsn > Vgsn >

Vdsn < Vdsn >

VDD

Idsp
Vin Vout
Idsn

4: DC and Transient Response CMOS VLSI Design Slide 

 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn

Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn

VDD

Idsp
Vin Vout
Idsn

4: DC and Transient Response CMOS VLSI Design Slide

 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn

Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn

VDD
Vgsn = Vin Idsp
Vin Vout
Vdsn = Vout Idsn

4: DC and Transient Response CMOS VLSI Design Slide

 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn
Vout < Vin - Vtn Vout > Vin - Vtn

VDD
Vgsn = Vin Idsp
Vin Vout
Vdsn = Vout Idsn

4: DC and Transient Response CMOS VLSI Design Slide

 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vgsp < Vgsp <

Vdsp > Vdsp <

VDD

Idsp
Vin Vout
Idsn

4: DC and Transient Response CMOS VLSI Design Slide 

 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp

Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp

VDD

Idsp
Vin Vout
Idsn

4: DC and Transient Response CMOS VLSI Design Slide 

 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp

Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp

VDD
Vgsp = Vin - VDD Vtp < 0 Idsp
Vin Vout
Vdsp = Vout - VDD Idsn

4: DC and Transient Response CMOS VLSI Design Slide 

 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp
Vout > Vin - Vtp Vout < Vin - Vtp

VDD
Vgsp = Vin - VDD Vtp < 0 Idsp
Vin Vout
Vdsp = Vout - VDD Idsn

4: DC and Transient Response CMOS VLSI Design Slide 

Voltage Input/Output
 I-V Characteristics
‰ Make pMOS wider than nMOS such that βn = βp
Vgsn5

Vgsn4
Idsn

Vgsn3
-Vdsp
-VDD Vgsn2
Vgsp1 Vgsn1
Vgsp2 0 VDD
Vgsp3 Vdsn

Vgsp4 -Idsp

Vgsp5

4: DC and Transient Response CMOS VLSI Design Slide 

 Load Line Analysis
‰ Vin = 0

Vin0

Idsn, |Idsp|

Vin0
VDD
Vout

4: DC and Transient Response CMOS VLSI Design Slide 

 Load Line Analysis
‰ Vin = 0.2VDD

Vin1
Idsn, |Idsp|

Vin1
VDD
Vout

4: DC and Transient Response CMOS VLSI Design Slide 

 Load Line Analysis
‰ Vin = 0.4VDD

Idsn, |Idsp|

Vin2
Vin2

VDD
Vout

4: DC and Transient Response CMOS VLSI Design Slide 

 Load Line Analysis
‰ Vin = 0.6VDD

Idsn, |Idsp|

Vin3
Vin3

VDD
Vout

4: DC and Transient Response CMOS VLSI Design Slide 

 Load Line Analysis
‰ Vin = 0.8VDD

Vin4
Idsn, |Idsp|

Vin4
VDD
Vout

4: DC and Transient Response CMOS VLSI Design Slide 

 Load Line Analysis
‰ Vin = VDD

Vin0 Vin5

Vin1
Idsn, |Idsp|

Vin2
Vin3
Vin4
VDD
Vout

4: DC and Transient Response CMOS VLSI Design Slide 

 Load Line Summary

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

4: DC and Transient Response CMOS VLSI Design Slide 

 DC Transfer Curve
‰ Transcribe points onto Vin vs. Vout plot

VDD
Vin0 Vin5
A B

Vout
Vin1 Vin4
C

Vin2 Vin3
Vin3 Vin2 D
Vin4 Vin1 E
0 Vtn VDD/2 VDD+Vtp
VDD VDD
Vout Vin

4: DC and Transient Response CMOS VLSI Design Slide 

Load curves for Vdd=2.5V
DC Transfer curve for Vdd=2.5V
 Operating Regions
‰ Revisit transistor operating regions

Region nMOS pMOS VDD

A B
A
Vout
B C
C
D D
E
0
E Vtn VDD/2 VDD+Vtp
VDD
Vin

4: DC and Transient Response CMOS VLSI Design Slide 

 Operating Regions
‰ Revisit transistor operating regions

Region nMOS pMOS VDD

A B
A Cutoff Linear
Vout
B Saturation Linear C
C Saturation Saturation
D Linear Saturation D
E
0
E Linear Cutoff Vtn VDD/2 VDD+Vtp
VDD
Vin

4: DC and Transient Response CMOS VLSI Design Slide

 Region Operation

4: DC and Transient Response CMOS VLSI Design Slide 

 Beta Ratio
‰ If βp / βn ≠ 1, switching point will move from VDD/2
‰ Called skewed gate
‰ Other gates: collapse into equivalent inverter
VDD
βp
= 10
βn
Vout 2
1
0.5
βp
= 0.1
βn

0
VDD
Vin

4: DC and Transient Response CMOS VLSI Design Slide 

Variation of Switching threshold with
beta ratio
 Noise Margins
‰ How much noise can a gate input see before it does
not recognize the input?

Output Characteristics Input Characteristics

VDD
Logical High
Output Range VOH Logical High
Input Range
NMH
VIH
Indeterminate
VIL Region
NML
Logical Low
Logical Low VOL Input Range
Output Range
GND

4: DC and Transient Response CMOS VLSI Design Slide 

 Logic Levels
‰ To maximize noise margins, select logic levels at

Vout

VDD

β p/β n > 1

Vin Vout

Vin
0
VDD

4: DC and Transient Response CMOS VLSI Design Slide

 Logic Levels
‰ To maximize noise margins, select logic levels at
– unity gain point of DC transfer characteristic
Vout

Unity Gain Points

VDD
Slope = -1
VOH

β p/β n > 1

Vin Vout

VOL
Vin
0
Vtn VIL VIH VDD- VDD
|Vtp|

4: DC and Transient Response CMOS VLSI Design Slide

 MOSFET Circuit at DC – Problem 1
The MOSFET in the circuit shown has Vt = 1V,
kn’= 100μA/V2 and λ = 0. Find the required
values of W/L and of R so that when
vI=VDD=+5 V, rDS=50 Ω and vo= 50 mV.

vI = VGS = 5 V , vo = VDS = 0.05 V

VDS 0.05
rDS = 50 Ω = ⇒ ID = = 0.001 A = 1 mA
ID 50

VDD − vo 5 − 0.05
R= = = 4.95 k Ω
ID 1

31
 MOSFET Circuit at DC – Problem 1 (cont’)

VDS < VGS − Vt ⇒ triode region

W ⎡ V 2
⎤
I D = kn ⎢(VGS − Vt )VDS −
' DS
L⎣ 2 ⎥⎦

W ⎡ 0.05 2
⎤
1 = 100 × 10 −3
⎢ ( 5 − 1) × 0.05 −
L⎣ 2 ⎥⎦

W
= 50
L