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Simple Interfacing
4 HIGH 4 V
HIGH
Typical 3.5 V
3 3 V
TTL voltage 2.4 V
profile 2 2.0 V TTL 2 V
Undefined Undefined
1 1 V
0.8 V
LOW 0.4 V
Typical 0.1 V LOW
GND GND
GND to 0.8 V. Also, a HIGH input must be in 70–100 percent of VDD (10 V in this exam-
the range from 2.0 to 5.5 V. The unshaded ple) as a HIGH. Likewise, any voltage within 0
section from 0.8 to 2.0 V on the input side is to 30 percent of VDD is regarded as a LOW in-
the undefined area, or indeterminate region. put to ICs in the 4000 and 74C00 series.
Therefore, an input of 3.2 is a HIGH input. An Typical output voltages for CMOS ICs are
input of 0.5 V is considered a LOW input. An shown in Fig. 5-2(a). Output voltages are nor-
input of 1.6 V is in the undefined region and mally almost at the voltage rails of the power
should be avoided. Inputs in the undefined re- supply. In this example, a HIGH output would
gion yield unpredictable results at the output. be about 10 V while a LOW output would be
Expected outputs from the TTL inverter are about 0 V or GND.
shown on the right in Fig. 5-1. A typical LOW The 74HC00 series and the newer 74AC00
output is about 0.1 V. A typical HIGH output and 74ACQ00 series operate on a lower-
might be about 3.5 V. However, a HIGH out- voltage power supply (from 2 to 6 V) than
put could be as low as 2.4 V according to the the older 4000 and 74C00 series CMOS ICs.
voltage profile diagram in Fig. 5-1. The HIGH The input and output voltage characteristics are
output depends on the resistance value of the summarized in the voltage profile diagram in
load placed at the output. The greater the load Fig. 5-2(b). The definition of HIGH and LOW
Data sheets for current, the lower the HIGH output voltage. for both input and output on the 74HC00,
ICs at www. The unshaded section on the output voltage 74AC00, and 74ACQ00 series is approxi-
onsemi.com or side in Fig. 5-1 is the undefined region. Sus- mately the same as for the 4000 and 74C00
www.ti.com. pect trouble if the output voltage is in the series CMOS ICs. This can be seen in a com-
undefined region (0.4 to 2.4 V). parison of the two voltage profiles in Figs.
The voltages given for LOW and HIGH 5-2(a) and (b).
logic levels in Fig. 5-1 are for a TTL device. The 74HCT00 series and newer 74ACT00,
These voltages are different for other logic 74ACTQ00, 74FCT00, and 74FCTA00 series
families. of CMOS ICs are designed to operate on a 5-V
The 4000 and 74C00 series CMOS logic power supply like TTL ICs. The function of the
families of ICs operate on a wide range of 74HCT00, 74ACT00, 74ACTQ00, 74FCT00,
power supply voltages (from 3 to 15 V). and 74FCTA00 series of ICs is to interface be-
The definition of a HIGH and LOW logic level tween TTL and CMOS devices. These CMOS
for a typical CMOS inverter is illustrated in ICs with a “T” designator can serve as direct
Fig. 5-2(a). A 10-V power supply is being used replacements for many TTL ICs.
in this voltage profile diagram. A voltage profile diagram for the 74HCT00,
The CMOS inverter shown in Fig. 5-2(a) 74ACT00, 74ACTQ00, 74FCT00, and
will respond to any input voltage within 74FCTA00 series CMOS ICs is drawn in
HIGH
8 V HIGH 8 V
7V 4000
and
6 V 74C00 6 V
Undefined series Undefined
4000 and 74C00
series CMOS
4 V 4 V
voltage profile
3V
2 V CMOS LOW 2 V
LOW
0.05 V
GND GND
(a)
INPUT OUTPUT
VOLTAGE VOLTAGE
5 V 5 V
4.9 V
HIGH
4 V 74HC00 HIGH 4 V
3.5 V 74AC00
and
3 V 74ACQ00 3 V 74HC00 and
Undefined series Undefined 74AC00 series
2 V 2 V CMOS voltage
profile
1 V 1V CMOS LOW 1 V
LOW
GND 0.1 V GND
(b)
INPUT OUTPUT
VOLTAGE VOLTAGE
5 V 5 V
Typical 4.7 V HIGH
74HCT00
4 V 74ACT00 4 V
4.3 V
HIGH 74ACTQ00
3 V
74FCT00
3 V
“T” series CMOS
74FCTA00 profile
series Undefined
2 V 2.0 V 2 V
Undefined
1 V CMOS LOW 1 V
0.8 V 0.3 V
LOW
Typical 0.2 V
GND GND
(c)
Fig. 5-2 Defining CMOS input and output voltage levels. (a) 4000 and 74C00
series voltage profile. (b) 74HC00, 74AC00, and 74ACQ00 series
voltage profile. (c) 74HCT00, 74ACT00, 74ACTQ00, 74FCT00,
74FCTA00 series voltage profile.
Fig. 5-2(c). Notice that the definition of LOW CMOS ICs (see Figs. 5-1 and 5-2(c)). The out-
and HIGH at the input is the same for these “T” put voltage profiles for all the CMOS ICs are
CMOS ICs as it is for regular bipolar TTL ICs. similar. In summary, the “T” series CMOS ICs
This can be seen in a comparison of the input have typical TTL input voltage characteristics
side of the voltage profiles of TTL and the “T” with CMOS outputs.
then the margin of safety between it and the Fig. 5-4 TTL input logic levels showing noise
undefined region is 0.6 V (0.8 0.2 0.6 V). margin.
4 V 4 V
HIGH
HIGH
3 V Noise margin (0.4 V) 3 V
2 V 2 V
2.4 V
2.0 V 0.8 V Noise margin (0.4 V)
1 V 0.4 V 1 V
LOW
LOW
GND GND
3 V 3 V
3.5 V
2 V
1.5 V 2 V
0.05 V
1 V 1 V
LOW Noise margin (1.5 V) LOW
Comparing TTL
GND GND
and CMOS noise
margins Fig. 5-3 Defining and comparing TTL and CMOS noise margins.
5-2 Other Digital IC Schottky TTL (LS-TTL) is 20 and for the 4000
Specifications series CMOS it is considered to be about 50.
Digital logic voltage levels and noise margins Another way to look at the current character-
were studied in the last section. In this section, istics of gates is to examine their output drive
other important specifications of digital ICs and input loading parameters. The diagram in
will be introduced. These include drive capabil- Fig. 5-5(a), on the next page, is a simplified
ities, fan-out and fan-in, propagation delay, and view of the output drive capabilities and input
power dissipation. load characteristics of a standard TTL gate.
A standard TTL gate is capable of handling
Drive Capabilities 16 mA when the output is LOW (IOL) and 400
A bipolar transistor has its maximum wattage A when the output is HIGH (IOH). This seems
and collector current ratings. These ratings de- like a mismatch until you examine the input
termine its drive capabilities. One indication of loading profile for a standard TTL gate. The Drive
output drive capability of a digital IC is called its input loading (worst-case conditions) is only capabilities
fan-out. The fan-out of a digital IC is the number 40 A with the input HIGH (IIH) and 1.6 mA Fan-out
of “standard” inputs that can be driven by the when the input is LOW (IIL). This means that
gate’s output. If the fan-out for standard TTL the output of a standard TTL gate can drive
gates is 10, this means that the output of a single 10 inputs (16 mA/1.6 mA 10). Remember,
gate can drive up to 10 inputs of the gates in the these are worst-case conditions and in actual
same subfamily. A typical fan-out value for stan- bench tests under static conditions these input
dard TTL ICs is 10. The fan-out for low-power load currents are much less than specified.
4 V IOH IIH 4 V
HIGH
400 A 40 A HIGH
3 V 3 V
2 V 2 V
1 V 1 V
IOL IIL
LOW 16 mA 1.6 mA LOW
GND GND
(a)
A summary of the output drive and input of CMOS ICs one of the preferred logic
loading characteristics of several popular fami- families for new designs. The newer FAST
lies of digital ICs is detailed in Fig. 5-5(b). TTL logic series also has many desirable
Look over this chart of very useful information. characteristics that make it suitable for new
You will need this data later when interfacing designs.
TTL and CMOS ICs. The load represented by a single gate is
Fan-in Notice the outstanding output drive capa- called the fan-in of that family of ICs. The input
bilities of the FACT series of CMOS ICs (see loading column in Fig. 5-5(b) can be thought of
Fig. 5-5(b)). The superior drive capabilities, as the fan-in of these IC families. Notice that
low power consumption, excellent speed, and the fan-in or input loading characteristics are
great noise immunity make the FACT series different for each family of ICs.
Standard TTL
www.ti.com.
LS-TTL
(a)
4 V IOH IIH 4 V
HIGH
400 A 40 A HIGH
3 V 3 V
2 V 2.4 V 2 V
2.0 V
1 V 0.8 V 1 V
0.4 V IOL IIL
LOW 8 mA 1.6 mA LOW
GND GND
(b)
Fig. 5-6 Interfacing LS-TTL to standard TTL problem. (a) Logic diagram of
interfacing problem. (b) Voltage and current profiles for visualizing
the solution to the problem.
40
20
10
0
AS AC F S ALS LS HC Standard C 4000
TTL CMOS TTL TTL TTL TTL CMOS TTL CMOS series
CMOS
Logic Families
(b)
Propagation Fig. 5-7 (a) Waveforms showing propagation delays for a standard TTL inverter.
delays (b) Graph of propagation delays for selected TTL and CMOS families.
Emitter coupled shown in Fig. 5-7(a) for a standard TTL 7404 speed operation, the ECL (emitter coupled
logic (ECL) inverter IC. logic) and the developing gallium arsenide
The typical propagation delay for a standard families are required.
TTL inverter (such as the 7404 IC) is about
Power 12 ns for the LOW-to-HIGH change while only Power Dissipation
dissipation 7 ns for the HIGH-to-LOW transition of the Generally, as propagation delays decrease
input. (increased speed), the power consumption and
Representative minimum propagation delays related heat generation increase. Historically, a
are summarized on the graph in Fig. 5-7(b). standard TTL IC might have a propagation
The lower the propagation delay specification delay of about 10 ns compared with a propaga-
for an IC, the higher the speed. Notice that the tion delay of about 30 to 50 ns for a 4000 series
AS-TTL (advanced Schottky TTL) and AC- CMOS IC. The 4000 CMOS IC, however,
CMOS are the fastest with minimum propaga- would consume only 0.001 mW, while the stan-
tion delays of about 1 ns for a simple inverter. dard TTL gate might consume 10 mW of
The older 4000 and 74C00 series CMOS fam- power. The power dissipation of CMOS
ilies are the slowest families (highest propa- increases with frequency. So at 100 kHz, the
gation delays). Some 4000 series ICs have 4000 series gate may consume 0.1 mW of
propagation delays of over 100 ns. In the past, power.
TTL ICs were considered faster than those The speed versus power table in Fig. 5-8
manufactured using the CMOS technology. compares in graphic form several of the mod-
FACT series Currently, however, the FACT CMOS series ern TTL and CMOS families. The vertical axis
CMOS ICs rival the best TTL ICs in low propagation on the graph represents the propagation delay
delays (high speed). For extremely high- (speed) in nanoseconds while the horizontal
5-3 MOS and CMOS ICs MOS) type. Metal oxide semiconductor chips
are smaller, consume less power, and have a
MOS ICs better noise margin and higher fan-out than
The enhancement type of metal oxide semicon- bipolar ICs. The main disadvantage of MOS
ductor field-effect transistor (MOSFET) forms devices is their relative lack of speed.
the primary component in MOS ICs. Because
of their simplicity, MOS devices use less space CMOS ICs
on a silicon chip. Therefore, more functions per Complementary symmetry metal oxide semicon- Complementary
chip are typical in MOS devices than in bipolar ductor (CMOS) devices use both P-channel and symmetry
ICs (such as TTL). Metal oxide semiconductor N-channel MOS devices connected end to end. metal oxide
technology is widely used in large scale inte- Complementary symmetry metal oxide semi- semiconductor
gration (LSI) and very large scale integration conductor ICs are noted for their exceptionally ICs
(VLSI) devices because of this packing density low power consumption. The CMOS family of
on the chip. Microprocessors, memory, and ICs also has the advantages of low cost, sim-
clock chips are typically fabricated using MOS plicity of design, low heat dissipation, good
technology. Metal oxide semiconductor circuits fan-out, wide logic swings, and good noise-
are typically of either the PMOS (P-channel margin performance. Most CMOS families of PMOS
MOS) or the newer, faster NMOS (N-channel digital ICs operate on a wide range of voltages. NMOS
Vin Vout
ABOUT ELECTRONICS
Locks with Memory. Intel chips used in safe locks offer 500
billion possible combinations. But in case someone still wants VSS (GND)
to try, the lock records the number of unsuccessful attempts to
Fig. 5-9 CMOS structure using
open it. P-channel and N-channel
MOSFETs in series.
INPUT OUTPUT
100 k
TTL INPUT OUTPUT
CMOS
(a)
5 V (a)
5 V 5 V
10 k
INPUT OUTPUT
INPUT OUTPUT
TTL
CMOS
100 k
(b)
(b)
Switch-to-CMOS 5 V 5 V
Fig. 5-11 Switch-to-CMOS interfaces.
interfaces (a) Active-LOW switch interface with
pull-up resistor. (b) Active-HIGH switch
INPUT OUTPUT interface with pull-down resistor.
TTL
illustrates an active HIGH switch feeding a
CMOS inverter. The 100-k pull-down resistor
makes sure the input to the CMOS inverter is
330
near ground when the input switch is open. The
resistance value of the pull-up and pull-down
resistors is much greater than those in TTL
(c) interface circuits. This is because the input
loading currents are much greater in TTL than
Switch-to-TTL Fig. 5-10 Switch-to-TTL interfaces. (a) Simple in CMOS. The CMOS inverter illustrated in
interfaces active-LOW switch interface.
Fig. 5-11 could be from the 4000, 74C00,
(b) Active-LOW switch interface using
pull-up resistor. (c) Active-HIGH switch 74HC00, or the FACT series of CMOS ICs.
interface using pull-down resistor.
Switch Debouncing
current required by a standard TTL gate may be The switch interface circuits in Figs. 5-10 and
as high as 1.6 mA (see Fig. 5-5(b)). 5-11 work well for some applications. How-
Two switch-to-CMOS interface circuits are ever, none of the switches in Figs. 5-10 and 5-11
drawn in Fig. 5-11. An active LOW input were debounced. The lack of a debouncing cir-
switch is drawn in Fig. 5-11(a). The 100-k cuit can be demonstrated by operating the
pull-up resistor pulls the voltage to 5 V counter shown in Fig. 5-12(a). Each press of
when the input switch is open. Figure 5-11(b) the input switch should cause the decade (0–9)
Decade
counter OUTPUT
INPUT To find out more
about software
CLK switch debounc-
ing using a
BASIC stamp,
visit www.
stampsinclass.
(a)
com.
5 V
TTL
TTL decade
debouncing circuit counter OUTPUT
INPUT 10 k
CLK
10 k
(b)
Fig. 5-12 (a) Block diagram of switch interfaced to a decimal counter system. (b) Adding a
debouncing circuit to make the decimal counter work properly.
counter to increase by 1. However, in practice LOW. A Schmitt trigger can also change a
each press of the switch increases the count by slow-rising signal (such as a sine wave) into a
1, 2, 3, or sometimes more. This means that square wave.
several pulses are being fed into the clock The switch debouncing circuit in Fig. 5-13(b)
(CLK) input of the counter each time the switch will drive 4000, 74HC00, or FACT series
is pressed. This is caused by switch bounce. CMOS or TTL ICs. Another general-purpose
A switch debouncing circuit has been added to switch debouncing circuit is illustrated in Fig. Switch
the counting circuit in Fig. 5-12(b). The decade 5-13(c). This debouncing circuit can drive ei- debouncing
counter will now count each HIGH–LOW cycle ther CMOS or TTL inputs. The 7403 is an circuit
of the input switch. The cross-coupled NAND open-collector NAND TTL IC and needs pull-
gates in the debouncing circuit are sometimes up resistors as shown in Fig. 5-13(c). The ex-
called an RS flip-flop or latch. Flip-flops will be ternal pull-up resistors make it possible to have RS flip-flop or
studied later in greater detail. an output voltage of just about 5 V for a latch
Several other switch debouncing circuits are HIGH. Open-collector TTL gates with external Open-collector
illustrated in Fig. 5-13. The simple debouncing pull-up resistors are useful when driving TTL output
circuit drawn in Fig. 5-13(a) will only work on CMOS with TTL.
the slower 4000 series CMOS IC. The 40106 Another switch debouncing circuit using the
CMOS IC is a special inverter. The 40106 is a versatile 555 timer IC is sketched in Fig. 5-14.
Schmitt trigger inverter, which means it has a When pushbutton switch SW1 is closed (see Schmitt trigger
“snap action” when changing to either HIGH or point A on output waveform) the output toggles inverter
100 k
INPUT
OUTPUT
40106 To 4000 series
CMOS only
0.047 F
(a)
5 V
100 k 100 k
74HC00
OUTPUT
To 4000 series CMOS or
INPUT 74HC00 series CMOS or
7400 TTL or
FACT series CMOS
74HC00
(b)
5 V
1 k 1 k
7403
OUTPUT
To 4000 series CMOS or
INPUT 74HC00 series CMOS or
7400 TTL or
FACT series CMOS
7403
(c)
Switch Fig. 5-13 Switch debouncing circuits. (a) A 4000 series switch debouncing circuit. (b) General
debouncing purpose switch debouncing circuit that will drive CMOS or TTL inputs. (c) Another
circuits general-purpose switch debouncing circuit that will drive CMOS or TTL inputs.
from LOW to HIGH. Later when input switch for this circuit) the output toggles from HIGH
SW1 is opened (see point B on waveform) the to LOW.
output of the 555 IC remains HIGH for a delay The delay period can be adjusted for the
period. After the delay period (about 1 second switch debouncing circuit shown in Fig. 5-14.
2 Timer IC 3 L
(555)
Switch closed Delay
6
7
C2 10 F
5 1
.01 F C1
Fig. 5-14 Switch debouncing circuit using the 555 timer IC.
One method of adjusting the time delay is to at the output of the 555 IC. Increasing the ca-
change the capacitance value of C2. Decreas- pacitance value of C2 will increase the delay
ing the value of C2 will decrease the delay time time.
(a) (b)
10 15 V
OUTPUT 10 V 15 V
VDD
CMOS
CMOS Light = HIGH
INPUT 1 k
VSS 1 k VDD
CMOS
CMOS
INPUT Light = LOW
VSS
OUTPUT
(c) (d )
5 15 V
5 15 V
OUTPUT
VDD
CMOS CMOS
Light = HIGH
buffer
1 k
INPUT VDD
VSS4049 1 k CMOS CMOS
INPUT buffer
Light = LOW
VSS4050
OUTPUT
(e) (f )
5 V
7404 OUTPUT
INPUT Standard
TTL
A Light = HIGH
150
LED
Light = LOW
A OUTPUT
K
LED
150
7404 K
INPUT Standard
TTL
(g) (h)
Simple
CMOS-to-LED Fig. 5-15 Simple CMOS- and TTL-to-LED interfacing. (a) CMOS active HIGH. (b) CMOS
active-LOW. (c) CMOS active HIGH, supply voltage 10 to 15 V. (d) CMOS
interfacing active LOW, supply voltage 10 to 15 V. (e) CMOS inverting buffer to LED
Simple TTL-to- interfacing. (f ) CMOS noninverting buffer to LED interfacing. (g) TTL active-HIGH.
LED interfacing (h) TTL active-LOW.
5 V
5 V
H
HIGH
LOW
H
(a) (b)
5 V
150
A
OUTPUT
Light = HIGH
K
CMOS
2N3904
or
NPN C
TTL
33 k B
INPUT
(a)
5 V
150
A
OUTPUT
Light = LOW
K
CMOS
2N3906
or
PNP E
TTL
33 k B
INPUT
(b)
Interfacing to Fig. 5-17 Interfacing to LEDs using a transistor driver circuit.
LEDs using a (a) Active-HIGH output using a NPN transistor driver.
transistor drive (b) Active-LOW output using a PNP transistor driver
circuit (simplified logic probe).
150 150
INPUT 2N3906
2N3904
NPN C PNP E
33 k 33 k
B B
Q1 Q2
(c) E C
Fig. 5-17 (cont.) Interfacing to LEDs using a transistor driver circuit. (c) HIGH-LOW indicator circuit
(simplified logic probe).
5 V
47
#49 bulb
2 V, 60 mA
Light = HIGH
FACT 2N3904
or NPN
C
TTL
3.9 k B
INPUT
Interfacing to an
Fig. 5-18 Interfacing to an incandescent lamp using a transistor driver incandescent
circuit. lamp
400 A 1 A HIGH
4 V 4 V
HIGH
3.5 V
3 V 3 V
2.4 V Undefined
2 V 2 V
Undefined 1.5 V
1 V 1 V
0.8 V LOW
LOW 16 mA 1 A
GND GND
(a)
5 V
1 k
VCC VDD
Standard TTL CMOS
TTL CMOS
INPUT OUTPUT
GND VSS
(b)
Fig. 5-20 TTL-to-CMOS interfacing. (a) TTL output and CMOS input profiles TTL-to-CMOS
for visualizing compatibility. (b) TTL-to-CMOS interfacing using a interfacing
pull-up resistor.
2.2-k pull-up resistor. The pull-up resistor is method of solving this problem is illustrated in
being used to pull the TTL HIGH up near 5 V Fig. 5-21(d). The 74HCT00 series of CMOS 74HCT00 series
so that it will be compatible with the input volt- ICs is specifically designed as a convenient of CMOS ICs
age characteristics of CMOS ICs. interface between TTL (or NMOS) and CMOS.
In Fig. 5-21(b), a CMOS inverter (any Such an interface is implemented in Fig.
series) is driving an LS-TTL inverter directly. 5-21(d) using the 74HCT34 noninverting IC.
Complementary symmetry metal oxide semi- The 74HCT00 series of CMOS ICs is widely
conductor ICs can drive LS-TTL and ALS-TTL used when interfacing between NMOS devices
(advanced low-power Schottky) inputs: most and CMOS. The NMOS output characteristics
CMOS ICs cannot drive standard TTL inputs are almost the same as for LS-TTL.
without special interfacing. The modern FACT series of CMOS ICs has FACT series of
Manufacturers have made interfacing easier excellent output drive capabilities. For this rea- CMOS ICs
by designing special buffers and other interface son FACT series chips can drive TTL, CMOS,
chips for designers. One example is the use of NMOS, or PMOS ICs directly as illustrated in
the 4050 noninverting buffer in Fig. 5-21(c). Fig. 5-22(a). The output voltage characteristics
The 4050 buffer allows the CMOS inverter to of TTL do not match the input voltage profile
have enough drive current to operate up to two of 74HC00, 74AC00, and 74ACQ00 series
standard TTL inputs. CMOS ICs. For this reason, a pull-up resistor is
The problem of voltage incompatibility from used in Fig. 5-22(b) to make sure the HIGH out-
TTL (or NMOS) to CMOS was solved in put voltage of the TTL gate is pulled up near the
Fig. 5-20 using a pull-up resistor. Another 5-V rail of the power supply. Manufacturers
2.2 k
VCC VDD
Low power (LS)TTL LS CMOS
CMOS
INPUT TTL OUTPUT AC TTL
GND VSS
(a) FACT
Bipolar TTL
5 V HC & HCT
(a) NMOS
PMOS
VDD VCC
Any CMOS LS Low power TTL FACT
CMOS TTL OUTPUT
INPUT
VSS GND 5V
(b) 4.7 k
5 V
TTL AC
5 V
5V
(d )
Fig. 5-21 Interfacing TTL and CMOS when both use FAST
HCT
a common 5-V power supply. (a) Low- AS/ALS
ACT
power Schottky TTL to CMOS interfacing FCT
using a pull-up resistor. (b) CMOS to low- FCTA
power Schottky TTL interfacing. (c) CMOS (c) ACTQ
to standard TTL interfacing using a CMOS
buffer IC. (d ) TTL to CMOS interfacing Fig. 5-22 Interfacing FACT with other families.
using a 74HCT00 series IC. (a) FACT driving most other TTL and
CMOS families. (b) TTL-to-FACT
interfacing using a pull-up resistor.
(c) TTL-to-“T” CMOS ICs.
produce “T”-type CMOS gates that have the
input voltage profile of a TTL IC. TTL gates
can directly drive any 74HCT00, 74ACT00, put has a voltage swing from about 0 to almost
74FCT00, 74FCTA00, or 74ACTQ00 series 10 V. Figure 5-23(b) shows an open-collector
CMOS IC, as summarized in Fig. 5-22(c). TTL buffer and a 10-k pull-up resistor being
Interfacing CMOS devices with TTL devices used to translate the lower TTL to the higher
takes some added components when each oper- CMOS voltages. The 7406 and 7416 TTL ICs
ates on a different voltage power supply. Figure are two inverting, open-collector (OC) buffers.
5-23 shows three examples of TTL-to-CMOS Interfacing between a higher-voltage CMOS
and CMOS-to-TTL interfacing. Figure 5-23(a) inverter and a lower-voltage TTL inverter is
CMOS buffer shows the TTL inverter driving a general- shown in Fig. 5-23(c). The 4049 CMOS buffer
purpose NPN transistor. The transistor and is used between the higher-voltage CMOS
associated resistors translate the lower-voltage inverter and the lower-voltage TTL IC. Note
TTL outputs to the higher-voltage inputs needed that the CMOS buffer is powered by the lower-
to operate the CMOS inverter. The CMOS out- voltage (5 V) power supply in Fig. 5-23(c).
5 V 10 k
VDD CMOS
CMOS (higher voltage)
VCC 1 K VSS OUTPUT
Any TTL TTL
INPUT 2N3904
GND
(a)
10 V
5 V
10 k
VCC OC
VCC VDD CMOS
Any TTL TTL TTL
CMOS (higher voltage)
buffer
INPUT OUTPUT
GND 7406 VSS
GND 7416
(b)
10 V 5 V
(c)
Fig. 5-23 Interfacing TTL and CMOS when each use a different
power supply voltage. (a) TTL-to-CMOS interfacing using
a driver transistor. (b) TTL-to-CMOS interfacing using an
open collector TTL buffer IC. (c) CMOS-to-TTL interfacing
using a CMOS buffer IC.
Looking at the voltage and current profiles Several techniques are used to interface be-
(such as in Fig. 5-20(a)) is a good starting point tween different logic families. These include
when learning about or designing an interface. the use of pull-up resistors and special interface
Manufacturers’ manuals are also very helpful. ICs. Sometimes no extra parts are needed.
5 V
Piezo
OUTPUT
buzzer
Standard
TTL
INPUT
FACT
(a)
5 V
Piezo
OUTPUT
buzzer
TTL
or 2N3904
NPN C
FACT
2.2 k B
INPUT
(b)
Fig. 5-24 Logic device to buzzer interfacing. (a) Standard TTL or
FACT CMOS inverter driving a piezo buzzer directly.
(b) TTL or CMOS interfaced with buzzer using a
transistor driver.
5 V
Relay
N.C.
OUTPUT
To controlled
circuit
N.O.
TTL
2N3904
or C
NPN
FACT
2.2 k B
INPUT
Fig. 5-25 TTL or CMOS interfaced with a relay using a transistor driver circuit.
5 V
OUTPUT
Logic device
to motor
interfacing
Logic device 12 V
to solenoid TTL
interfacing or 2N3904
FACT NPN C DC
2.2 k motor
B
INPUT
(a)
5 V
OUTPUT
12 V
TTL
or 2N3904
FACT NPN C
2.2 k B
INPUT
E
Solenoid
(b)
Fig. 5-26 Using a relay to isolate higher voltage/current circuits from digital circuits. (a) Interfacing
TTL or CMOS with an electric motor. (b) Interfacing TTL or CMOS with a solenoid.
3 4 Emitter pin 1
(a)
Fig. 5-27 (a) The 4N25 optoisolator pin out and six-pin DIP.
150 10 k
1
TTL or
FACT
INPUT OUTPUT
2 5
4
Optoisolator
(b)
12 V
5 V
1 k
150
Piezo
1 OUTPUT
TTL or buzzer
FACT
INPUT
2 5
4
Optoisolator
(c)
5 V 12 V 12 V
DC
150 10 k OUTPUT
motor
TIP31
1
TTL or NPN C
FACT 2.2 k Q1
INPUT
2 5 B
E
4
Optoisolator
(d)
Fig. 5-27 (cont.) (b) Basic optoisolator circuit separates 5 V and 12 V circuits. (c) Optoisolator driving
piezo buzzer. (d) Optoisolator isolating low-voltage digital circuit from high
voltage/current motor circuit.
(a)
(b)
Fig. 5-28 (a) Solid-state relay—small PC-mounted package.
(b) Solid-state relay—heavy duty package.
relays can be purchased to handle a variety of spikes and noise. Traditionally, electromag-
outputs included in either ac or dc loads. The netic relays have been used for isolation, but
output circuitry in a solid-state relay may be optoisolators and solid-state relays are an inex-
more complicated than that shown in Fig. pensive and effective alternative when interfac-
5-27(d). ing with digital circuits. A typical optoisolator,
Several examples of solid-state relay pack- shown in Fig. 5-27(a), contains an infrared-
ages are shown in Fig. 5-28. The unit in Fig. emitting diode that activates a phototransistor.
5-28(a) is a smaller PC-mounted unit. The larger If you are building an interface project using
bolted-on solid-state relay has screw terminals the parallel port from an IBM-compatible or
and can handle greater ac currents and voltages. PC, you will want to use optoisolators between
In summary, it is common to isolate digital your circuits and the computer. The PC paral-
circuitry from some devices because of high lel-port outputs and inputs operate with TTL
operating voltages and currents or because of level signals. Good isolation protects your
dangerous feedback in the form of voltage computer from voltage spikes and noise.
Black
(PWM)
servo
(a) motor
5 V
INPUT
Pulse Red
generator 1 msec
50 Hz
Black
(PWM)
servo
(b) motor
5 V
INPUT
Pulse Red
generator 2 msec
50 Hz
Black
(PWM)
servo
(c) motor
V
Pot
feed back Output
INPUT SIGNAL
Control shaft
Electronics
dc
motor
(d)
Fig. 5-29 Controlling the angular position of a hobby servo motor using pulse-width modulation (PWM).
(NOTE: Some hobby servos rotate in the opposite direction as the pulse width increases.)
0
h. 2
2p c
d °
5 V 18
p
Ste
(a)
L1
L1 Stepper
motor
L2
L2
(b)
L1
L2
Stator 2
Stator 1 Simulations of
Stator 1 poles several types of
Shaft motors including
a stepper motor
can be found at
Motorola’s web-
site.
Stator 2 Poles
Rotor
(permanent magnet)
(c)
Fig. 5-30 (a) Typical four-wire stepper motor. (b) Schematic of four-wire
bipolar stepper motor. (c) Simple exploded view of typical
permanent magnet type stepper motor.
1 1 0 1 0
For more 2 0 1 1 0
information on 3 0 1 0 1
controlling servo 4 1 0 0 1
and stepper
1 1 0 1 0
motors with a
BASIC stamp, 2 0 1 1 0
visit www.
stampsinclass. Sequence: Sequence:
com. down chart CW rotation up chart CCW rotation
(a)
L1 L1 L2 L2
L1 L2
L1
L2
Stepper
motor
(b)
Fig. 5-31 (a) Bipolar control sequence chart. (b) Test circuit for hand checking a four-
wire bipolar stepper motor.
instance, suppose you want the motor from inputs to the coils as specified by step 2, then
Fig. 5-30(a) to rotate at 600 rpm. This means step 3, and then step 4, and so on, the motor ro-
that the motor rotates 10 revolutions per second tates by stepping in a CW direction. If you re-
(600 rpm/60 sec 10 rev/sec). You would have verse the order and sequence upward on the
to send the code from the control sequence in Fig. control sequence chart in Fig. 5-31(a) the mo-
5-31(a) to the stepper motor at a frequency of tor reverses and rotates by stepping in a CCW
200 Hz (10 rev/sec 20 steps per rev 200 Hz). direction. The circuit in Fig. 5-31(b) is an im-
practical interface circuit but can be used for
Stepper Motor Interfacing hand testing a stepper motor.
Consider the simple test circuit in Fig. 5-31(b) A practical bipolar stepper motor interface is
which could be used to check a bipolar stepper based on the MC3479 stepper motor driver IC
motor. The single-pole double-throw (SPDT) from Motorola. The schematic diagram in
switches are currently set to deliver the volt- Fig. 5-32(a) details how you might wire the
ages defined by step 1 on the control sequence MC3479 driver IC to a bipolar stepper motor.
chart in Fig. 5-31(a). As you change the voltage The MC3479 IC has a logic section that generates
Logic Motor
7 drivers 2 L1 Stepper
clock Clk L2
15 L2 motor
L3
Half step 1 14 L2
9
Full/Half L4
Full step 0
Bias GNDs
6 4 5 12 13
47 k
(a)
Step L1 L2 L3 L4
1 1 0 1 0
2 1 1 1 0
3 0 1 1 0
4 0 1 1 1
5 0 1 0 1
Step L1 L2 L3 L4
6 1 1 0 1
1 1 0 1 0 7 1 0 0 1
2 0 1 1 0 8 1 0 1 1
3 0 1 0 1 1 1 0 1 0
4 1 0 0 1 2 1 1 1 0
1 1 0 1 0 3 0 1 1 0
2 0 1 1 0 4 0 1 1 1
(b) (c)
Fig. 5-32 (a) Using the MC3479 Stepper Motor Driver IC to interface with a bipolar stepper motor.
(b) Control sequence of the MC3479 IC in the full-step mode. (c) Control sequence for the
MC3479 IC in the half-step mode.
the proper control sequence to drive a bipolar in Fig. 5-30 rotates 18 for each clock pulse
stepper motor. The motor driver section has a (each single step). In the half-step mode, the
drive capability of 350 mA per coil. Each step stepper motor rotates half of a regular step or
of the motor is triggered by a single positive- only 9 per clock pulse. The control sequence
going clock pulse entering the CLK input (pin used by the MC3479 IC in the full-step mode is
7) of the IC. One input control sets the direction shown in chart form in Fig. 5-32(b). Note that this
of rotation of the stepper motor. A logic 0 at the is the same control sequence used in Fig. 5-31(a).
CW CCW input to the MC3479 allows CW ro- The control sequence used by the MC3479 IC in
tation while a logic 1 input at pin 10 changes to the half-step mode is detailed in chart form in Fig.
CCW rotation of the stepper motor. 5-32(c). These control sequences are standard for
The MC3479 IC also has a 苶 苶/Half input
Full bipolar or two-phase stepper motors and are built
(pin 9) which can change the operation of the into the logic block of the MC3479 stepper motor MC 3479
IC from stepping by full steps or half steps. In driver IC. Specialized ICs such as the MC3479 Stepper motor
driver IC
the full-step mode, the stepper motor featured stepper motor driver are usually the simplest and
Digital compass
EGR valve
ABS wheel
position sensor
speed sensor
Throttle position
sensor
Ride height
sensor
Tachometer
pickup
sensor
Camshaft
timing sensor
Steering sensor
Camshaft
timing sensor
Transmission
shift position
sensor
V
Magnetic field
(perpendicular to sensor)
Bias
Voltage
N
Hall-effect sensor
(a)
e
tag
Vol ator
ul
reg dc Amplified
Hall V
Amp Hall voltage
S
(b)
Fig. 5-35 Hall-effect sensor. (a) Sensor produces a small voltage proportional to the
strength of the magnetic field. (b) Adding a voltage regulator and dc amplifier
to produce a more useable Hall-effect sensor.
The output voltage of the Hall-effect sensor ear output voltage such as the sensor sketched
is small and is commonly amplified to be more in Fig. 5-35(b). Others are designed to operate
useful. A Hall-effect sensor with a dc amplifier as switches. A commercial Hall-effect switch
and voltage regulator is sketched in Fig. 5-35(b). is featured in Fig. 5-36. The Hall-effect switch
The output voltage is linear and proportional to detailed in Fig. 5-36 is the 3132 bipolar Hall-
the strength of the magnetic field. effect switch produced by Allegro Microsystems,
Inc. The three-lead package in Fig. 5-36(a)
Hall-Effect Switch shows that pins 1 and 2 are for connecting the
Hall-effect devices are produced in rugged IC external power supply ( to Vcc and to
packages. Some are designed to generate a lin- ground). Pin 3 is the output of this bouncefree
SUPPLY
GROUND
OUTPUT
Pinning is shown viewed from branded side.
(a)
Reverse-battery
1 VCC protection
Voltage
regulator REG.
Schmitt-trigger
threshold detector
Hall-effect 2 OUTPUT
sensor
3 GROUND
(b)
Fig. 5-36 Allegro Microsystem’s 3132 Bipolar Hall-effect switch. (a) Pin diagram.
(b) Functional block diagram.
switch. The pinout in Fig. 5-36(a) is correct The two most important characteristics of a
when viewing the 3132 Hall-effect switch from magnetic field are its strength and its polarity
the printed side (branded side) of the IC pack- (South or North poles of magnet). Both of these
age. A functional block diagram of Allegro Mi- characteristics are used in the operation of the
crosystem’s 3132 Hall-effect switch is drawn in bipolar 3132 Hall-effect switch. To demon-
Fig. 5-36(b). Notice that the symbol for the strate the operation of the bipolar Hall-effect
Hall-effect sensor is a rectangle with an X in- switch study the circuit in Fig. 5-37(a) includ-
side. Added to the sensor are several sections ing the 3132 IC. An output indicator LED with
that convert the analog Hall-effect device into a 150- limiting resistor has been added at the
digital switch. The Schmitt-trigger threshold output of the IC.
detector produces a snap-action bouncefree In Fig. 5-37(a), the south pole of the magnet
output needed for digital switching. Its output approaches the branded side (side with print-
is either HIGH or LOW. The open-collector ing) of the IC causing the internal NPN transis-
output transistor is included so the IC can drive tor turn to ON. This causes pin 3 of the IC to
a load up to 25 mA continuously. drop LOW causing the LED to light.
150
3132
Hall-effect switch OUTPUT
NPN transistor ON
PIN 3 is LOW
LED is ON
3
2
VCC
1
S
INPUT
S pole
N
of magnet
(a)
+5 V
150
3132
Hall-effect switch OUTPUT
NPN transistor OFF
PIN 3 is HIGH
LED is OFF
3
2
VCC
1
N
INPUT
N pole
S
of magnet
(b)
Fig. 5-37 Controlling 3132 Hall-effect switch with opposite poles of a magnet
(a) Turning ON switch with S pole. (b) Turning OFF switch with N pole.
Pull-up resistor
33k- for CMOS
10k- for TTL
Output
3
CMOS
or
TTL
2
VCC
1
Fig. 5-38 Interfacing Hall-effect switch IC with either TTL or CMOS.
In Fig. 5-37(b), the north pole of the magnet a built-in permanent magnet. A sketch of typical
approaches the branded side (side with print- gear-tooth sensing IC and gear is shown in
ing) of the IC causing the internal NPN transis- Fig. 5-39. The South pole of the permanent mag-
tor turn OFF. This causes pin 3 of the IC to go net produces a magnetic field that varies with the
HIGH and the LED does not light. position of the gear. When a gear-tooth moves
The 3132 Hall-effect switch was bipolar be- into position to shorten the air gap, the field gets
cause it required a S pole and then a N pole to stronger and the Hall-effect sensor switches.
make it toggle between ON and OFF. Unipolar Gear-tooth sensors are commonly used in me-
Hall-effect switches are also available which turn chanical systems including automobiles to count
ON and OFF by just increasing (switch ON) and the position, rotation, and speed of gears.
decreasing (switch OFF) the magnetic field
strength and not changing polarity. One such
unipolar Hall-effect switch is the 3144 by Allegro
Microsystems, Inc. The 3144 unipolar Hall-effect
switch is a close relative the the 3132 bipolar
Hall-effect switch you have already studied. The
unipolar 3144 IC shares the same pinout diagram Gear
[Fig. 5-36(a)] and functional block diagram [Fig.
5-36(b)] as the bipolar 3132 Hall-effect switch. Air gap
The 3144 Hall-effect switch features a snap- Half-effect
South sensors
action digital output. The 3144 IC also features
an NPN output transistor that will sink 25mA. Permanent
The Hall-effect switch IC drawn in Fig. 5-38 Magnet
Answer the following questions. Hall-effect sensor in the 3132 causing the
LED to (light, not light).
73. A Hall-effect sensor is a(n) 79. Refer to Fig. 5-41(b). Output transistor
(magnetically, optically)-activated device. of the IC is turned (ON,
74. Hall-effect devices such a OFF) and the output at pin 3 goes
(gear-tooth sensors, thermocouples) and (HIGH, LOW) when the
switches are commonly used in automo- north pole of a magnet approaches the
biles because they are reliable, inexpensive, Hall-effect sensor in the 3132 causing
and can operate under severe conditions. the LED to not light.
75. Refer to Fig. 5-40. The semiconductor 80. Refer to Fig. 5-36. The snap-action caus-
material shown with the X on it is called ing a digital output (either HIGH or
the (electromagnet, Hall-effect LOW) from the IC is caused by the
sensor). (dc amplifier, Schmitt-trigger)
76. Refer to Fig. 5-40. Moving the permanent section of the IC.
magnet closer to the Hall-effect sensor 81. Hall-effect switches are small, bounce-
increases the magnetic field causing the free, rugged, and (inexpen-
output voltage to (decrease, sive, very expensive).
increase). 82. The open-collector of the NPN driver
77. Refer to Fig. 5-41. The 3132 Hall-effect IC transistor used in both the 3132 and 3144
is a (bipolar, unipolar) switch. Hall-effect switches requires the use a
78. Refer to Fig. 5-41(a). Output transistor of (pull-up, transition) resistor
the IC is turned ON and the output at pin when sending digital signals to either
3 goes (HIGH, LOW) when CMOS or TTL logic devices.
the south pole of a magnet approaches the
Vout
S
150
OUTPUT
3132 LED
Hall-effect switch
3
2
VCC
1
S
(a)
+5 V
150
OUTPUT
3132 LED
Hall-effect switch
3
2
VCC
1
N
(b)
GN
1 D
VCC 0 4
740
VCC
A
B
C
D
(a)
5 V 5 V
14 14
1 3 1
INPUT A
2 3
INPUT B 6 2
4 IC1 IC2
INPUT C
5 LED1
INPUT D R1
7 7
PARTS LIST
IC1 7400 quad 2-input NAND gate
IC2 7432 quad 2-input OR gate
LED1 Red diffused T–1-3/4 light-emitting diode
R1 1/2 W, 150 , 10% resistor
(b)
Fig. 5-42 Troubleshooting problem. (a) Testing a faulty circuit mounted on a PC board. (b) Schematic
diagram of four-input NAND circuit.
a schematic similar to the one shown in 1. Set the logic probe to TTL and connect
Fig. 5-42(b). Look at the circuit and schematic the power.
and determine the logic diagram. From that 2. Test nodes 1 and 2 (see Fig. 5-42(a)).
you can determine the Boolean expression Result: Both are HIGH.
and truth table. You will find that in this ex- 3. Test nodes 3 and 4. Result: Both are
ample, two NAND gates are feeding an OR LOW. Conclusion: Both ICs have
gate. This is equivalent to the four-input power.
NAND function. 4. Test the four-input NAND circuit’s
The fault in the circuit in Fig. 5-42(a) is unique state (inputs A, B, C, and D are all
shown as an open circuit in the input to the OR HIGH). Test at pins 1, 2, 4, and 5 of the
gate. Now let’s troubleshoot the circuit to see 7400 IC. Results: All inputs are HIGH
how we find this fault. but the LED still glows and indicates a
5-12 Interfacing the Servo and black Vss or GND) of the power
(BASIC Stamp Module) wires.
2. Load the PBASIC text editor program
Programmable devices are very common in
(version for the BS2 IC) into the PC.
modern digital electronics. This section will ex-
Type your PBASIC program describing
plore interfacing of the BASIC Stamp 2 micro-
the ‘Servo Test 1. A PBASIC program
controller module with a simple servo.
titled ‘Servo Test 1 is listed in the shaded
Review section 5-9 on servo motors. Hobby
box.
servo motor operation is summarized in Fig.
3. Attach a serial cable between the PC and
5-29. Notice the use of pulse-width modulation
the BASIC Stamp 2 development board
(PWM) to control the angular position of the
(such as the Board of Education by
servo motor. In this section, you will program a
Parallax, Inc.).
BASIC Stamp 2 microcontroller module to act
4. With the BASIC Stamp 2 module turned
as the PWM pulse generator sketched in Figs.
on, download your PBASIC program
5-29(a), (b), and (c). Notice in Fig. 5-29 that the
from the PC to BS2 module using the
positive pulse widths are 2 msec for fully CCW
RUN command.
rotation, 1 msec for fully CW rotation, or 1.5
5. Disconnect the serial cable from the BS2
msec for centering of the servo’s output shaft.
module.
Consider the hobby servo motor connected
6. Observe the rotation of the servo output
to the BASIC Stamp 2 module in Fig. 5-43.
shaft. The PBASIC program stored in
This is a test circuit to rotate the servo (1) fully
EEPROM program memory in the BASIC
CCW, (2) fully CW, and (3) to finally center the
Stamp 2 module will restart each time the
output shaft.
BS2 IC is turned on.
The procedure for solving the logic problem
with the use of the BASIC Stamp 2 module is PBASIC Program—ServoTest 1
detailed below. The steps in wiring and pro-
Consider the PBASIC program titled ‘ServoTest
gramming the BASIC Stamp 2 module are:
1. Lines 1 and 2 both begin with an apostrophe (‘)
1. Refer to Fig. 5-43. Wire the hobby servo meaning these are remark statements. Remark
motor to port P14 of the BASIC Stamp 2 statements are used to clarify the program and are
module. Note the color coding (red Vdd not executed by the microcontroller. Line 3 is a
Serial port
Do
wnlo
ad
pro g
ra
m
Black
Vss
Fig. 5-43 Hobby servo motor connected to a BASIC Stamp 2 module for testing.
line of code to declare a variable that will be used C is a variable name that will hold a word length
later in the program As an example, L3 reads value (16 bits). The 16-bit variable C can hold a
C VAR Word. This tells the microcontroller that range of values from 0 to 65535 in decimal.
END L16
5 V
INPUT
SW 1
LED1
R1 OUTPUT
R2
Hall-effect switch
IC
3
Vout
2
N
VCC
1
Fig. 5-47 Art for chapter review questions 5-64, 5-65, and 5-69. magnet