Chapter 5

BJT as switches and amplifiers

Microelectronic Circuit Design

Richard C. Jaeger
Travis N. Blalock
(c) 2015 McGraw-Hill Education.
All rights reserved
Adapted by Huy Q. Le, DUT-UD
 Chapter Goals

• Investigate simple transistor implementations of

the inverter and other logic circuits

• Bipolar switching circuits

Chap 5 - 2
Operation Regions of Bipolar Transistors

Binary Logic
States

• Saturation Region
(Closed Switch)

• Cutoff Region
(Open Switch)

Chap 5 - 3
Brief History of Digital Electronics

• Digital electronics can be found in many applications in the

form of microprocessors, microcontrollers, PCs, DSPs, and
an uncountable number of other systems.
• The design of digital circuits has progressed from resistor-
transistor logic (RTL) and diode-transistor logic (DTL) to
transistor-transistor logic (TTL) and emitter-coupled logic
(ECL) to NMOS and now complementary MOS (CMOS)
• The density and number of transistors in microprocessors
has increased from approximately 2300 in the 1971 4-bit
4004 microprocessor to 400 million in more recent P4 chips
and are projected to reach ten billion transistors by 2015

Chap 5 - 4
Device Feature Size

• Feature size reductions

enabled by process
innovations.
• Smaller features lead to
more transistors per unit
area and therefore
higher density.

Chap 5 - 5
Rapid Increase in Density of Microelectronics

Chap 5 - 6
Ideal Logic Gates

• Binary logic gates are the most common style of

digital logic

• The output will consist of either a 0 (low) or a 1 (high)

– (Positive Logic Convention)

• The most basic digital building block is the inverter

Chap 5 - 7
The Ideal Inverter

• The ideal inverter has the following voltage transfer

characteristic (VTC) and is described by the following symbol

Chap 5 - 8
Logic Level Definitions

• An inverter operating with power supplies at V+ and 0 V can be

implemented using a switch with a resistive load
• The switch could be a mechanical device such as a wall switch or
relay, a vacuum tube, or an MOS or bipolar transistor
Chap 5 - 9
 Logic Level Definitions: Voltage Levels

• VL – The nominal voltage corresponding to a low-

logic state at the output of a logic gate for vi = VH
• VH – The nominal voltage corresponding to a
high-logic state at the output of a logic gate for
vi = VL
• VIL – The maximum input voltage that will be
recognized as a low input logic level
• VIH – The maximum input voltage that will be
recognized as a high input logic level
• VOH – The output voltage corresponding to an
input voltage of VIL
• VOL – The output voltage corresponding to an
input voltage of VIH

Chap 5 - 10
 Noise Margins

• Noise margins represent “safety

margins” that prevent the circuit
from producing erroneous outputs
in the presence of noisy inputs
• Noise margins are defined for low
and high input levels using the
following equations:

NML = VIL – VOL

NMH = VOH –
VIH

Chap 5 - 11
 Review of Boolean Algebra

A Z A B Z A B Z A B Z A B Z
0 1 0 0 0 0 0 0 0 0 1 0 0 1
1 0 0 1 1 0 1 0 0 1 0 0 1 1
NOT 1 0 1 1 0 0 1 0 0 1 0 1
Truth Table
1 1 1 1 1 1 1 1 0 1 1 0
ZA
OR AND NOR NAND
Truth Table Truth Table Truth Table Truth Table
Z  A B Z = AB Z = A +B Z = AB Chap 5 - 12
The Saturating Bipolar Inverter

• One of the most basic circuits for

BJT logic gates is the saturating
bipolar inverter

• The resistor “pulls” the output

high when vI is low, and the
output goes to vCE = VCESAT
when vI is high

Chap 5 - 13
 Saturating Bipolar Inverter: Design Example

* Design a saturating bipolar inverter such that the collector saturation voltage is
0.1 V with a collector current of 10 A. Find the base current required to achieve
these specifications given the following:  F  20;  R  0.1; VT  25mV
* Design:
 1    R 1 
• First, check the minimum VCE: VCEMIN  VT ln    VT ln    0.06 V
R   R 
VCESAT   0.1V 
• Next find :   exp  exp  54.6
 VT  0.025V 
 
  F   20 
• Finally, solving for IB: 1  1 
IC  R  10A  0.154.6 
IB     2.92 A
 F 1 1  20 1 1 

  R  
   1  
  54.6 
 11 
Chap 5 - 14
Saturating Bipolar Inverter
Load Line Visualization

• The following is a typical

load line characteristic for a
saturating bipolar inverter

Chap 5 - 15
Saturating Bipolar Inverter
Switching Characteristics

• An important effect of switching

in BJTs is that the excess base
current required to drive the BJT
into saturation results in extra
stored charge in the base region.
This charge must be removed
before the BJT can be turned off.
• This delay is called the storage
time (tS)
• The figures show typical
switching characteristics for
various values of reverse base
current

Chap 5 - 16
Saturating Bipolar Inverter
Switching Characteristics (cont.)
• The storage time delays can be calculated using the following
expressions:
 
 
 I BF  I BR 
t S   S ln
 iCMAX 
   I BR 
 F 
 F  F   R R 
S 
1   R F
where F and R are the forward and reverse common-base current
gains, F and R are the forward and reverse transit times, and S is the
storage time constant. IBF and IBR are the forward and reverse values
of base current.

Chap 5 - 17
 Transistor-Transistor Logic (TTL)
Circuit Prototype
• TTL has been a workhorse technology in digital systems
such for many years
• The basic structure for the TTL inverter is shown below

Chap 5 - 18
TTL Prototype
Output Low Logic State (vI = VH)

The output ranges from VOL = 0.15 V to VOH = 5 V

Chap 5 - 19
TTL Prototype
Output High Logic State (vI = VL)

Chap 5 - 20
TTL Prototype: Power Dissipation

• The power the TTL inverter dissipates for a low output is:

• The power the TTL inverter dissipates for a high output is:

Chap 5 - 21
TTL Prototype: VIH, VIL, and Noise Margins
• The figure shows where VIL
and VIH occur, and they can
be approximated by the
following expressions using
standard TTL values:
VIL  0.7  VCESAT1  0.66 V
VOH  V H  VT  V H  5 V
VIH  VBESAT 2  0.8 V
VOL  VL  VCESAT 2  0.15 V
NM L  0.66  0.15  0.51 V
NM H  5.0  0.8  4.2 V

Chap 5 - 22
TTL Prototype: Fanout Limitations

• For NMOS, CMOS, and

ECL gates, fanout was not
investigated in detail since
the input currents to these
gates were considered to be
zero. However, this is not
the case for TTL as seen in
the figure.

Chap 5 - 23
TTL Prototype: Fanout Limitations (cont.)

• For a TTL gate find:

a) the fanout limit (N) for VCESAT2 less than 0.1 V
b) the input current iIH and fanout limit for vI = vH
assuming R1 = 2
Use the following:
 F  40
 R  0.25
VCESAT1  0.04 V
VBESAT  0.8 V
VBE  0.7 V

Chap 5 - 24
TTL Prototype: Fanout Limitations (cont.)

• First find N for vO = VL:

5 VBESAT  vI 5  0.8  0.1 V
iIL     1.03 mA
RB 4 k
VCC  vO
iC  iR  N (iIL )   N (iIL )  2.45mA  N (1.03mA)
RC

 0.1V 
• Next find the max iC:   exp  54.6
0.025V 
1
1
0.2554.6
 FOR  40  17.7
20
1
0.33354.6

Chap 5 - 25
TTL Prototype: Fanout Limitations (cont.)

• Continuing:
iB2  1.09 mA

• The collector current can be no greater than

 FORiB2  19.3 mA

• Which give the following:

2.45mA  N 1.03mA  19.3 mA  N  16

Chap 5 - 26
TTL Prototype: Fanout Limitations (cont.)

• But now computing for vO = VH, it can be found

the the fanout (N) is 7. Therefore, the max fanout
for the circuit is 7
• Part (b) analysis - Finding iIH and N with R1 = 2

 5  0.8  0.7 
iIH   RiB1  2    1.75 mA
 4 

5V  N (2k)(1.75mA)  1.5V  N  1

Chap 5 - 27
TTL Logic: Standard 7400 Series Gates

• One problem of the TTL inverter prototype

described so far is that the dynamic response is
asymmetrical due to the use of a resistive load to
pull the output up and a BJT to pull the output
down

• Another problem is that the fanout capability is

highly sensitive to the value of R

Chap 5 - 28
TTL Logic: 7400 Series Inverter
• The classic approach to fixing these problems appears in
the implementation of the 7404 hex inverters in a dual-in-
line package (DIP)

Chap 5 - 29
TTL Logic: 7400 Series Inverter

• In the 7404 TTL inverter

circuit, Q4 replaces the
passive resistive load pull-up
in the prototype TTL inverter
to make it an active pull-up
circuit

• Q3 and D1 ensure that the Q4

is turned off when Q2 is on

Chap 5 - 30
TTL Logic: 7400 Series Inverter - VH

Assume vI  VL  0.15 V

VH  VCC  iB 4 RC  vBE 4  vD1

VH  5  0  0.7  0.7  3.6 V

Chap 5 - 31
TTL Logic: Current Available to Saturate Q2

* Assume vI  VH  3.6 V
VL  VCESAT 2  0.15 V

iB 2  iE 3  iRE  iC 3  iB 3  iRE
iB 2  2.57 mA

Chap 5 - 32
TTL Logic: Inverter Power Consumption

POL  POH
P   5.03 mW
2

Chap 5 - 33
TTL Logic
Propagation Delay and Power Delay Product

Simulation of Inverter Delay • The analysis of

propagation delay for
TTL gates is difficult
due to the number of
transistors involved,
so the results can be
estimated through
simulation.
 PHL  6 ns  PLH  14 ns
6 14
P   10 ns
2
PDP  5mW 10ns  50 pJ

Chap 5 - 34
TTL Logic: VTC and Noise Margins

• The figure shows the

VTC simulation
results for the TTL
inverter
• Using the results
from the simulation,
the noise margins
can be calculated as

Chap 5 - 35
TTL Logic: Standard TTL Fanout Limitations

• The active pull-up circuitry drastically improves

the fanout capabilities of the TTL inverter

• However, due to process variations, and the

requirement for the device to operate over a range
of temperatures, N is specified to be less than 10

Chap 5 - 36
TTL Logic: Functions in TTL

• The basic structure for the TTL NAND gate:

Chap 5 - 37
TTL Logic: NAND Gates

• The parallel input

can be applied to
create multiple input
NAND gates as seen
in the complete
circuit schematic for
the 7410 three-input
NAND gate

Chap 5 - 38
TTL Logic: NAND Gate Structure

• Multiple input NAND gates use a merged

transistor structure to save silicon area, since the
input BJTs share their emitters and collectors

Chap 5 - 39
TTL Logic: Other Gate Designs

TTL AND-OR- Low-power TTL

Invert NAND gate

Chap 5 - 40