Low Power VLSI Circuits and

Systems

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Why Low Power

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 Why Low Power
• Increasing transistor count
• Higher speed of operation
• Greater device leakage currents
Increased process parameter variability due to
aggressive device size scaling has created
problems in yield, reliability, and testing.

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Power Dissipation

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 Power Dissipation
• Power dissipation is measured commonly in terms of two
types of metrics:
1. Peak power: Peak power consumed by a particular device is
the highest amount of power it can consume at any time.
The high value of peak power is generally related to failures
like melting of some interconnections and power-line
glitches.
2. Average power: Average power consumed by a device is the
mean of the amount of power it consumes over a time
period. High values of average power lead to problems in
packaging and cooling of VLSI chips.
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Sources of Power Dissipations

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I1 is the reverse-biased p–n junction diode leakage current
I2 is the reverse-biased p–n junction current
I3 is the sub threshold leakage current
I4 is the oxide tunneling current(reduction due to oxide thickness)
I5 is the gate current(hot carrier injection)
I6 is the gate-induced drain leakage current 7
 MOS Transistors
• The base semiconductor material used for the fabrication of
MOS integrated circuits is Silicon
Metal: Aluminum
Oxide: Sio2
Semiconductor : Silicon family
• Patterned layers of the three conducting materials: Metal, Poly
silicon, and diffusion.
• Fabrication involves a series of photolithographic techniques
and chemical processes involving oxidation of silicon, diffusion
of impurities into the silicon and deposition and etching of
aluminum, poly on the silicon to provide interconnection.

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 MOS Fabrication Technology
• Metal–oxide–semiconductor (MOS) fabrication is the
process used to create the integrated circuits (ICs)
• Wafer Fabrication
• Oxidation
• Mask Generation
• Photolithography
• Diffusion
• Deposition

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 CMOS Fabrication
• N-well Process
• P-Well Process
• Twin-Tub Process
• SOI Process

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The n-Well Process

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 The p-Well Process
• P-well fabrication steps are similar to an n-well
process, except that a pwell is implanted to
form n-transistors rather than an n-well

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 Twin-Tub Process
In the twin-tub process, the starting material is either an
n+ or p+ substrate with a lightly doped epitaxial layer,
which is used for protection against latch-up. The
process is similar to the n-well process, involving the
following steps:
• Tub formation
• Thin oxide construction
• Source and drain implantations
• Contact cut definition
• Metallization
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Twin-Tub Process

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 Short-Channel Effects

The channel length L is usually reduced to increase both

the speed of operation and the number of components
per chip.

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Channel Punch Through

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Electrical Characteristics of MOS transistors

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MOS Inverters

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Transfer Characteristics and Noise Margins

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 MOS Inverter Configurations
• Pull up device as Resistor
• Pull up device as nMOS Depletion mode trans
• Pull up device as nMOS Enhancement mode
trans
• Pull up device as pMOS transistor

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Comparison of the Inverters

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 Inverter Ratio in Different Situations

• An nMOS Inverter Driven by Another Inverter

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An nMOS Inverter Driven Through Pass
Transistors

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Switching Characteristics

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 Driving large capacitance loads
• Super buffers
• BiCMOS inverters
• Buffer Sizing

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Super buffers

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Bi-CMOS inverters

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 MOS combinational circuits
• Pass Transistor Logic
• Gate Logic
• MOS Dynamic Circuits

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Pass Transistor Logic

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Realization of Pass transistor logic

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CPL,SRPL & DPL
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Gate Logic

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MOS Dynamic Circuits

Single Phase Dynamic Circuits

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Two Phase dynamic circuits

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Two Phase dynamic circuits

No Static Power
No Ratioed Logic

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Static /Dynamic

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Charge leakage

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Charge sharing

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Clock Skew

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 Sources of Power Dissipation
• Short circuit power dissipation
• Switching power dissipation
• Glitching power dissipation

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 Introduction
• Short-circuit power: Short-circuit power dissipation occurs when both the
nMOS and pMOS networks are ON. This can arise due to slow rise and
fall times of the inputs .
• Switching power dissipation: As the input and output values keep on
changing, capacitive loads at different circuit points are charged and
discharged, leading to power dissipation. This is known as switching
power dissipation. Until recently, this was the most dominant source of
power dissipation.
• Glitching power dissipation: Due to a finite delay of the logic gates, there are
spurious transitions at different nodes in the circuit. Apart from the
abnormal behavior of the circuits, these transitions also result in power
dissipation known as glitching power dissipation.

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Introduction

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Short-Circuit Power Dissipation

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Switching Power Dissipation

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Switching Activity of Static CMOS Gates

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Inputs Not Equiprobable

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Switching Activity for complex logic gates

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 Glitching Power Dissipation

Glitching power dissipation: Due to a finite delay of the logic gates, there are spurious
transitions at different nodes in the circuit. Apart from the abnormal behavior of the
circuits, these transitions also result in power dissipation known as glitching power
dissipation.
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 Leakage Power Dissipation
When the circuit is not in an active mode of operation, there is static power
dissipation due to various leakage mechanisms

Leakage’s are :

I1 is the reverse-biased p–n junction diode leakage current

I2 is the reverse-biased p–n junction current
I3 is the sub threshold leakage current
I4 is the oxide tunneling current(reduction due to oxide thickness)
I5 is the gate current(hot carrier injection)
I6 is the gate-induced drain leakage current

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p–n Junction Reverse-Biased Current

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Band-to-Band Tunneling Current

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 Sub threshold Leakage Current
• The sub threshold leakage current in CMOS circuits is due to carrier diffusion
between the source and the drain regions of the transistor in weak inversion

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Vth roll off

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Tunneling Through Gate Oxide

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Hot – carrier injection

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 Supply Voltage Scaling for Low Power

• The total power dissipation can be

represented by the simplified equation

• The switching power

• The glitching power
• The short-circuit power

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• Static Voltage Scaling (SVS) In this case, fixed supply voltages
are applied to one or more subsystems or blocks.
• Multilevel Voltage Scaling (MVS) This is an extension of the
SVS, where two or few fixed discrete voltages are applied to
different blocks or subsystems.
• Dynamic Voltage and Frequency Scaling (DVFS) This is an
extension of the MVS, where a large number of discrete
voltages are applied in response to the changing workload
conditions of the subsystems.
• Adaptive Voltage Scaling (AVS) This is an extension of the
DVFS, where a close loop control system continuously
monitors the workload and adjusts the supply voltage.
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Constant-Field Scaling

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Constant-Voltage Scaling

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Short-Channel Effects

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 Architectural-Level Approaches
• Architectural level to Register-transfer-Level.
3 level of approach

• Parallelism for low power

• Multi-core for low power
• Pipelining for low power

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 Parallelism for low power
• Parallel processing is traditionally used for the
improvement of performance at the expense
of a larger chip area and higher power
dissipation

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Pipelining

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Combining Parallelism with Pipelining

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Voltage Scaling Using High-Level
Transformations

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Loop unrolling

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Voltage scaling interfaces/ converter
placement

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• Floor Planning, Routing, and Placement
• Static timing analysis
• Power up and power down sequencing
• Clock frequency

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 Dynamic Voltage and Frequency Scaling

• DVFS has emerged as a very effective

technique to reduce CPU energy
• The technique is based on the observation
that for most of the real-life applications
• The energy drawn for the power supply, which
is the integration of power over time, can be
significantly reduced

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Variable Voltage Generator V(r)

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Adaptive Voltage Scaling

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