INTERNAL II IMPORTANT QUESTIONS

1. List the Various ADC and DAC Techniques.

DAC techniques:
 Binary Weighted resistor
 R-2R ladder type
ADC techniques:
 Successive Approximation ADC
 Flash ADC
2. Infer the various advantages of ADC and DAC in communication circuits.
 To convert the analog signals to digital and digital signals to analog signals.
 For long distance communications.
 For noise free communication.

3. Define resolution time and settling time in analog and digital converter.
RESOLUTION:

 Resolution is defined as the ratio of change in analog output voltage resulting from a change
of 1LSB at the digital input.
SETTLING TIME:

 Settling time represents the time it takes for the output to settle within a specified band ±(1/2)
LSB of its final value, after the change in digital input.
4. Draw the block diagram of PLL.

5. Discriminate RTL and DTL logic with example.

6. Classification of Digital logic family

7. Draw the inverter, NOR and NAND gate using NMOS

8. Define Fan out and Fan In.

Fan-in: The maximum number of input that can be applied to logic gates.
Fan-out: The Number of gate connected to the output of the driving gate.
9. Explain propagation delay in logic circuits.
Average delay time for the signal to propagate input to output. It is measured by nanosecond
1ns .
PD= tpLH + tpHL /2

10. Draw the NAND gate using DTL logic.

PART B

11. Explain the successive approximation ADC and its diagram.

The basic principle of this type of A/D converter is that the unknown analog input voltage is
approximated against an n-bit digital value by trying one bit at a time, beginning with the MSB. The
principle of successive approximation process for a 4-bit conversion is explained here.
This type of ADC operates by successively dividing the voltage range by half, as explained in the
following steps.
(1) The MSB is initially set to 1 with the remaining three bits set as 000. The digital
equivalent voltage is compared with the unknown analog input voltage.
(2) If the analog input voltage is higher than the digital equivalent voltage, the MSB is
retained as 1 and the second MSB is set to 1. Otherwise, the MSB is set to 0 and the
second MSB is set to 1. Comparison is made as given in step (1) to decide whether to
retain or reset the second MSB.

The above steps are more accurately illustrated with the help of an example.
 Let us assume that the 4-bit ADC is used and the analog input voltage is VA = 11 V.
when the conversion starts, the MSB bit is set to 1.
Now VA = 11V > VD = 8V = [1000]2
 Since the unknown analog input voltage VA is higher than the equivalent digital voltage
VD, as discussed in step (2), the MSB is retained as 1 and the next MSB bit is set to 1 as
follows
VD = 12V = [1100]2

Now VA = 11V < VD = 12V = [1100]2

 Here now, the unknown analog input voltage VA is lower than the equivalent digital
voltage VD. As discussed in step (2), the second MSB is set to 0 and next MSB set to 1 as
VD = 10V = [1010]2
Now again VA = 11V > VD = 10V = [1010]2
 Again as discussed in step (2) VA>VD, hence the third MSB is retained to 1 and the last
bit is set to 1. The new code word is
VD = 11V = [1011]2
 Now finally VA = VD , and the conversion stops.

It consists of a successive approximation register (SAR), DAC and comparator. The output of SAR is
given to n-bit DAC. The equivalent analog output voltage of DAC, VD is applied to the non-inverting
input of the comparator. The second input to the comparator is the unknown analog input voltage VA.
The output of the comparator is used to activate the successive approximation logic of SAR.
When the start command is applied, the SAR sets the MSB to logic 1 and other bits are made logic 0,
so that the trial code becomes 1000.

Advantages:
1 Conversion time is very small.
2 Conversion time is constant and independent of the amplitude of the analog input signal VA.

Disadvantages:
1 Circuit is complex.
2 The conversion time is more compared to flash type ADC.

12. Draw the circuit diagram of an inverter, two input NAND gate and two inputs NOR gate
using CMOS logic and explain their operation. (CO3,K3)

• CMOS(Complementary MOS) logic family uses both N-channel and P-channel MOSFET
devices.
• CMOS has greater complexity than PMOS and NMOS.
• However, the speed of operation is high and power dissipation is less in CMOS.
• CMOS also has more fan-out and better noise margin.
CMOS inverter:

For a HIGH input at VIN,

• The P-channel MOSFET(Q1) gets turned OFF, but the N-channel device(Q2) will be turned ON.
• This will drive the output Vo to be at Logic LOW.
• If LOW input is given at the input terminal VIN, it will turn ON on Q 1 and turn OFF Q2, making
the output to be HIGH.
CMOS NAND gate:
• The circuit shown below shows the circuit of the 2-input CMOS NAND gate.
• It has two p-channel MOSFETs (Q1, Q2) and two n-channel MOSFETs (Q3 and Q4).
• A and B are two inputs.
• The input A is given to the gate terminal of Q1 and Q3.
• The input B is given to the gate terminal of Q2 and Q4. The output is obtained from the terminal
VO.

• When both the inputs are given LOW input, it will turn ON Q1, Q2 and turn OFF the MOSFETs
Q3 and Q4.
• The output terminal is connected to the supply voltage VDD and the output will be HIGH.
• When either one of the input is high, for eg., Let us consider A is given HIGH input and B is
given LOW input.
• In this case, MOSFETs Q1 and Q4 get turned ON, whereas Q2 and Q3 are turned OFF as shown in
the diagram(b) below.
• This will make a path for the supply voltage to be connected to the load, making the output to be
HIGH.
 • If both the inputs A and B are HIGH inputs, which make the MOSFETs Q3, Q4 to be turned ON
and Q1, Q2 to be turned OFF.
• Thus the output is connected to the ground alone as shown below(c).
• Thereby, the output will be at LOW value.

CMOS NOR gate:

• For the LOW inputs at A and B, PMOS devices Q1 and Q2 will conduct, making the output to be
at logic HIGH.
• When any one of the input is LOW, it will produce a LOW output.
• If both A and B are given HIGH input, it will turn ON the PMOS devices Q 3 and Q4, making the
output voltage to be logic LOW.

13. Draw and explain Tri-State TTL inverter circuit diagram and explain its configurations

TTL

• Transistor-Transistor Logic belongs to the digital logic family.

• It consists of transistors at both input and output side, diodes and few resistors.

• Unlike Resistor-transistor logic and Diode transistor logic, both the logic function and amplifying
function are performed by the transistors.

• The TTL integrated circuits are very popular in different applications including computer
controls, consumer electronics, industrial control systems, etc.
• The following figure shows the circuit diagram of the 2-input TTL NAND gate.

• It has four transistors Q1, Q2, Q3 and Q4.

• Transistor Q1 has 2-inputs on the emitter side.

• Transistor Q3 and Q4 form the output side, called Totem pole output.

• The circuit of a 2-input TTL NAND gate may look complex.

• In the figure, diodes, DA and DB represent the 2-input emitter junction of transistor Q1.

• Diode DC represents the collector-base junction of transistor Q2.

• When both inputs A and B are low, both the diodes are forward biased.

• So the current due to the supply voltage +VCC = 5 V will go to the ground through R1 and the two
diodes DA and DB.

• The supply voltage gets dropped in the resistor R 1 and it will not be sufficient to turn ON the
transistor Q2.
 • With Q2 open, the transistor Q4 will also cut off.

• But the transistor Q3 is pulled high. Since Q 3 is an emitter follower, the output at the terminal will
also be HIGH, which is at logic 1.

• When any one input, either A or B is low, the diode with low input will be forward biased.

• The same operation will take place as explained above. In this case, the output will be HIGH.

• When both the inputs A and B are high, both the diodes at the emitter-base junction will be
reverse biased.

• The diode DC at the collector-base junction is forward biased.

• It will turn on the transistor Q2.

• With Q2 turned ON, transistor Q4 will also be turned ON.

• Both the transistors at the output side will conduct and so the output at terminal will have LOW
value, which is considered as logic 0.

Tri-state gate output:

• When the transistor Q3 is ON, the output at terminal Y is HIGH.

• The output is LOW when the transistor Q4 is turned ON.

• The first and second states are the normal operation of TTL.

• In the third state, both the transistors Q3 and Q4 are turned OFF, which results in neither LOW
nor HIGH output.