Design of 8-Bit Level Crossing

Analog To Digital Converter

Dr. Anil Kr. Gupta

Professor, ECE Department
NIT Kurukshetra
 Introduction

 Advantages

 Architecture and working principle

 Circuits and CMOS Implementation

 Simulation Results

 References
 Introduction

 Uniform Sampling vs LC Sampling

•ADC – Block Diagram
• Sampling

(a) uniform and (b) level crossing sampling

 Advantages of LC Sampling

• Low sampling rate required

• Bettar SNDR

• Only analog block is comparator. All other functional blocks are digital

• Magnitude quantization is replaced by time quantization

• Digital output is continuously available

• Faster response

• Suited for biomedical signals

.
Architecture and working principle

Architecture of LCADC
Architecture and working principle - contd

• Target Specs
 8-bit digital output
 8-bit timer output
 Analog input voltage range – 0 to 2.040V
Supply voltage – 0.8V
Low power dissipation (<500nW)
• Design Choices
 Comparators to operate in sub-threshold region
 Capacitive voltage dividers used
 Architecture chosen to minimise charging and discharging of capacitors
 VH = 2 LSB = 16mV, VCM = 1 LSB = 8mV, VL = 0 V
 Design to be implemented in 180nm CMOS using PDK of SCL Mohali
Architecture and working principle – contd.
Architecture and working principle - contd

• Working
•The input analog signal is directly applied to 1 bit DAC which converts it into VON
signal limiting the amplitude value within 2 LSB range from VH to VL. DAC is
controlled by the logic circuits which respond to the output signals of two
comparators. Lower comparator detects the direction of input signal by comparing
VON with VCM (DC signal with value equal to 1 LSB). The output of lower
comparator is given to RLC logic which generates CR and UD signal. Upper
comparator detects consecutive (CC) level crossing and generates CC pulse. Its
inputs are selected through MUX controlled by RLC logic. The OR gate takes CR
and CC pulse as inputs and generates CHANGE signal. CHANGE signal makes
the 8-bit up/down counter value change whenever level crossing occurs and also
resets the timer.
•The amplitude of VON signal is limited to 0-16 mV by the action of 1 bit DAC and
comparators. UD tells whether the analog input is rising (UD = 800mV) or falling
(UD = 0mV) and decides whether the counter counts up or down.
• The clock frequency determines the resolution of time measurement
 Circuits and CMOS Implementation

1. Comparator:

VDD = 0.8V, Input range 16mV, Gain 54 dB over BW of 3KHz

Circuits and CMOS Implementation - contd

Layout:

C0

Response:
Circuits and CMOS Implementation - contd

Power Dissipation:
Circuits and CMOS Implementation - contd

2. 1-bit DAC
Circuits and CMOS Implementation - contd

• Layout:

C2 C5

C1 C4

C0 C3

The transistor switches in DAC are controlled by logic signalsØ1, Ø2, Ø1L,
Ø2L Ø1H, Ø2H generated by DAC logic circuit. The middle branch of DAC
capacitor array is connected to left (or right) branch through M1 (or M2).
When VON is ranging in between VL and VM the left and right branch will
be connected to VH through M0 and M3 while they will be connected to VL
when VON is ranging between VM and VH.
Circuits and CMOS Implementation - contd

• Therefore one of the two side branches is always charged to predefined

voltage VH or VL. Now let us consider VON is between VM and VH and
middle branch is connected to left branch it means M1 and M5 are
conducting. Now if VON crosses VH, this generates a CC pulse which alters
the DAC logic control signals such that middle branch will be disconnected
from left branch. Simultaneously right branch will also be disconnected
from VL. The right branch will now be connected to the middle branch and
left branch to VL. Due to charge sharing effect VON is decreased by 1 LSB.
Switches will be readjusted VON crosses VH next time and the process
continues. Similar switching will happen with transistors M0 and M3 when
VON is ranging between VL and VM. The control signals are non-
overlapping to avoid direct connection of middle branch to VH or VL. Thus
the 1 bit DAC converts analog input signal to VON signal with amplitude
range 0 mV to 16 mV (2 LSB).
Circuits and CMOS Implementation - contd

• Transient Response:
Circuits and CMOS Implementation - contd

3. DAC Logic Circuit:

Circuits and CMOS Implementation - contd

• DAC Logic Transient Response:

4. RLC Logic Circuit

• RLC logic circuit controls the inputs of upper comparator through select signals ØUD and
Ø‟UDand also generates CR pulse whenever input signal changes direction.ØUDis given to
counter and DAC logic circuitas UD signal. It also helps in improving the output swing of
lower comparator.
Circuits and CMOS Implementation - contd

• RLC Logic circuit diagram and layout:

Circuits and CMOS Implementation - contd

• Transient Response of RLC Logic:

5. MUX:
• MUX provides the ability to switch inputs of upper comparator. It selects VON and
VH or VON and VL to be given to comparator based on value of select signals ØUD
and Ø‟UD. Comparator generates CC pulse signal which is applied to OR gate along
with CR pulse signal to generate the CHANGE signal.MUX was made using four
NMOS transistors .
Circuits and CMOS Implementation - contd

• Ckt. and layout:

Circuits and CMOS Implementation - contd

6. Up/Down Counter :
8-bit up/down counter was designed using T flip-flops, AND gates, OR gates and is driven by the
CHANGE signal as its clock. It gives the digital equivalent of the input signal whenever
level crossing occurs by counting up or down depending on the value of UD.
Circuits and CMOS Implementation - contd

7. Timer:
8-bit up counter is used to count the time interval between two successive level crossings.It was
designed using T flip-flops and AND gates. It records the value of time interval as number
of cycles of external clock (10 MHz) applied to the timer.
Circuits and CMOS Implementation - contd

8. Unity Gain Amplifier:

Reference voltages of 8 mV and 16 mV are generated on-chip using simple capacitor voltage
divider and unity gain amplifiers. Unity gain amplifiers prevent the capacitors from
discharging by providing isolation from load. Larger transistors were used to implement the
unity gain amplifiers as they are required to supply large current to load.
Circuits and CMOS Implementation - contd

9. Pin Descryption:

Purpose Number of pins

Input 3 ( VIN analog i/p , CLK , RESET )

Output 17 ( Q0-Q7 digital o/p, t0-t7 timer o/p, change )

Power 4 ( VDD,VDDO,GND,VSSO)
Circuits and CMOS Implementation - contd

10. Integrated Circuit Layout:

Circuits and CMOS Implementation - contd
 Simulation Results

• The circuit has been designed using 180 nm CMOS technology [from SCL] in cadence
virtuoso. DRC, LVS and PEX were performed using calibre tool. The pre and post layout
simulations were done using Hspice circuit simulator with supply voltage of 0.8 V. The
design has been tested by applying different inputs for different temperatures in the range 0-
70°C.
• Input signal amplitude range is limited to 1.8 V with resolution of 8mV.
• Power consumed by the LC-ADC was measured as a function of the slope of the input signal
keeping the amplitude of input constant equal to 0.4 V. In post- layout analysis the power
consumed varies from 90nW to 184nW.
pre-layout post-layout

200
180
160
140
power (nW)

120
100
80
60
40
20
0
0 1000 2000 3000 4000
slope of input signal (V/s)
Simulation Results - contd

Comparison of performance parameters

Parameter [3] [4] This work

Technology 0.18µm 0.18µm 0.18µm

Supply voltage 0.7V 0.8V 0.8V

Amplitude resolution 4-8 bits 6 bits 8 bits

Adaptive resolution Yes No No

Automatic calibration No No No

Full scale input (V) 1.4 1.6 1.8

Power consumption 25µW 313-582nW 90-184nW*

active area (mm2) 0.96 0.045 0.025*

*excluding the power consumed and area occupied by pads and reference voltage generation circuits
REFERENCES

1. Vaishali G., „Design and Implementation of Low Power 8-Bit Level

Crossing ADC‟ M.Tech. dissertation submitted at ECE Department, NIT
Kurukshetra, 2016.
2. M. Trakimas and S. Sonkusale, “A 0.8Vasynchronous ADC for energy
constrained sensing applications ,”in Proc. IEEE Custom
IntegratedCircuits Conf., pp. 173–176, September 2008.
3. Yongjia LI, Duan Zhao, Serdijn W.A, “ A sub microwatt Asynchronous
Level-Crossing ADC for Biomedical Applications,” IEEE Transactionson
Biomedical Circuits and systems, vol. 7, no. 2, pp. 149-157, April2013.
THANK YOU