Differential Amplifiers (part 2)

Sina Vafi
Faculty of Science and Technology
Input offset voltage of MOS differential pair
• If Q1 and Q2 are perfectly matched:
•Current I would split equally between Q1 and Q2 and Vo=0.
•Practically, Q1 and Q2 are mismatch. Then a dc output voltage Vo appears even
both input are grounded.
•Vo is called output dc offset voltage
•Definition: Input offset voltage (VOS): VOS=Vo/Ad
•If a voltage –VOS applies between input terminals of differential amplifier, the
output voltage will be zero
• Three factors contribute to the dc offset voltage
•Mismatch in load resistor
•Mismatch in W/L
•Mismatch in Vt

1. Mismatch in load resistor

R D
R D1  R D 
2
R D
R D2  R D  Sedra,6th edition,ISBN:9780199738519
2
 I R  I R 
VD1  VDD   RD  D  VD2  VDD   RD  D 
2 2  2 2 
Differential output voltage (VO):
VO=VD2-VD1=(I/2)∆RD
gm=I/VOV and |Ad|=gmRD and VOS=VO/Ad
 V  R 
VOS   OV  D 
 2  RD 
2. Effect of mismatch in (W/L)   W  
   
I I   L   Sedra,6th edition,ISBN:9780199738519

 W W 1  W I1  
      2 2   W  
 L 1 L 2  L   2  
  L  
 W W 1  W
        W  
 L 2 L 2  L     
I I   L  
I2  
VO=VD1-VD2=RD(I1-I2) 2 2   W  
 2  
|Ad|=gmRD   L  
I  (W / L) 
 
VOS 2 2( W / L )  I/2  VOV  (W / L) 
  and gm  then VOS    
2 gm VOV / 2  2  (W / L) 
 Vt Vt
3. Effect of mismatch in Vt: Vt1  Vt  Vt 2  Vt 
2
2 2
1 W V 
I1  kn  VGS  Vt  t 
2 L 2 
2
1 W  Vt 
 kn (VGS  Vt ) 2 1  
2 L  2( VGS  V )
t 

∆Vt<<2(VGS-Vt) or ∆Vt<<2VOV. Thus:

1 W 2  Vt  1 W 2 Vt 

I1  k n ( VGS  Vt ) 1   I 2  kn (VGS  Vt ) 1  
2 L  VGS  Vt  2 L  VGS  Vt

1 W I I Vt I Vt
kn (VGS  Vt )2  I  I2  I1  
2 L 2 2 VGS  Vt 2 VOV

Vo=RD (I1-I2)=RDI ∆Vt/VOV VOS=∆Vt

Three offset sources are working independently from each other

2 2
 VOV RD   VOV (W / L) 
VOS        (Vt )
2

 2 RD   2 W / L 
Input offset voltage of bipolar differential pair

Effect of mismatch in RC:

RC RC
RC1  RC  RC2  RC 
2 2
Sedra,6th edition,ISBN:9780199738519

 I  R   I  R 
VC1  VCC   RC  C  VC2  VCC    RC  C 
 2  2   2  2 

I
VO  VC 2  VC1   ( R C )
2

(I / 2)(R C )  R 
VOS  and Ad=gmRC | VOS | VT  C 
Ad  RC 
Effect of mismatch in emitter-base junction areas
•This effect appears as a mismatch in the scale current (IS):
I  IS I  IS
I S1  S  IS2  S 
2 2 2 2

• Assume: VBE1=VBE2 . Then the current I will split between Q1 and Q2 in proportion to
their IS values (IE  ISeVBE / VT / )

I  IS  I  IS   I  IS 

IE1  1  IE2  1  VO    RC
2  2IS  2  2IS   2  IS 

  IS 
V OS  V T   VT: Thermal voltage
 IS 
Overall VOS due to two abovementioned effects:
2 2
 R C   IS 
V OS   V T    V T 
 RC   IS 
2 2
 R C   I 
 VT     S 
 RC   IS 
 Input bias and offset currents of the bipolar pair:
• Assume Q1 and Q2 are perfectly matched.
I/2
I B1  I B2 
 1
• Mismatches in amplifier circuit and β makes
unequal input dc currents for two transistors

IOS  IB1  IB2 Sedra,6th edition,ISBN:9780199738519

 
1    2   
2 2
I 1 I 1   
I B1   1   I   
2   1  () / 2 2   1  2  IOS   
2(  1)   
I 1 I 1   
I B2   1  
2   1  () / 2 2   1  2 

IB1  IB2 I   
IB   thus IOS  I B  
2 2( 1)   
Differential amplifier with active load

Differential-to-single ended conversion

•The gain of differential amplifier is twice of normal amplifiers
with very low common-to-mode gain.
•Input common-mode appears between differential output due Sedra,6 edition,ISBN:9780199738519
th

to mismatch between elements or parameters of transistors.

•In multi-stage amplifiers, the first stage is differential. However,
differentially amplified signal is being converted to the single-ended amplifier to be
utilized for the next stages of the amplifier.
•Single-ended amplifier is achieved by ignoring drain current signal of Q1 and
eliminating its drain resistor and taking the output between drain of Q2 and ground.
Disadvantage:
Gain reduction due to ignoring drain current of Q1.
Solution:
Applying current-source instead of load resistance
Active loaded MOSFET differential pair
•Q1and Q2 are matched. Thus Vo=0 volt
•IQ3=IQ1=IQ2=I/2
•Q3 and Q4 form a current-source: IQ4=IQ3=I/2
•If Q3 and Q4 are matched (Vo)Q4=VDD-VSG3

1- Large signal analysis:

In practical applications:
•Transistors are not matched. Thus a dc current
appears at the output. Sedra,6 th edition,ISBN:9780199738519
•In case of no load: the current (I/2 generated from Q3)
flows to the output of Q4 and Q2.
•This causes a large deviation in the output voltage from the
Ideal value.
•dc bias voltage at the output node is defined by a feedback
Circuit rather than by simply relying on the matching of Q4 and Q3

2- Small-signal analysis
•The circuit is not symmetrical and it is impossible to use differential half-circuit technique
•Gain is achieved by calculation of short-circuit transconductance Gm and
output resistance (RO)
•Voltage difference between drain of Q1 and
ground is very small.
•A low resistance is observed from drain of Q3 and
ground, whose value is 1/gm3(Q3 operates as a diode)
•With the good approximation, circuit is symmetrical.
Therefore, we can assume a virtual ground appears
at the source of Q1 and Q2.
•Q3 has been replaced by its equivalent resistance
(1/gm3)||ro3

 v  1  Sedra,6th edition,ISBN:9780199738519

vg3  gm1 id  || ro3 || ro1 

 2  gm3 
 g  v 
ro3 and ro4 >> (1/gm3) v g 3   m1  id 
 g m 3  2 
Vg3 controls the drain current of Q4 , i.e. gm4 vg3
 vid 
Iro2=Iro4=0 i o  g v
m4 g3  g m2  
 2 
 g m4  vid   vid  Io=gmvid

io  g m1  
   g m2   Gm=gm
 g m3  2   2  gm1=gm2=gm3=gm4=gm
Output resistance calculation

1-Short-circuit the input

2- Put a voltage source at the output and
determine Ro=vx/ix

•Q2 is a CG transistor and its source resistance

Is equal to 1/gm1.
•Drain resistance of Q1: 1/gm3

Ro2=ro2+(1+gm2ro2)(1/gm1) Sedra,6th edition,ISBN:9780199738519

gm1=gm2=gm and gm2ro2>>1. Thus Ro2≈2ro2

v
ix  i  i  x
ro 4
vx vx vx Differential gain
 2i  2 
ro 4 R o 2 ro 4
vo
vx vx Ad   GmRo  gm(ro2 || ro4 )
ix   vid
ro 2 ro 4
v 1
R o  x  ro 2 || ro 4 ro2  ro4  ro Ad  gmro
ix 2
 Common-mode gain and CMRR

Sedra,6th edition,ISBN:9780199738519

• RSS can be equally split between Q1 and Q2:

Q1 and Q2 are common-source including 2RSS resistor 2RSS>>(1/gm)Q1,Q2
vsource ≈ vicm
• Ignore effect of ro1 and ro2. then i1=i2≈(vicm)/(2RSS)
• Ignore the body effect. Ro1=Ro2=ro+2RSS+2gmroRSS
ro1=ro2=ro and gm1=gm2=gm.
• Ro1>>(ro3||(1/gm3)) and Ro2>>ro4. Thus we can ignore Ro1 and Ro2 in finding total
resistance between each of the drain nodes and ground.
  1   1 
vg3  i1 || ro3  i 4  g m 4 v g 3  i1g m 4  || ro 3 
 gm3   g m3 
  1  
vo  (i 4  i 2 )ro 4  i1g m4  || ro3   i 2  ro 4
  g m3  

vo 1 ro4
Acm  
vicm 2RSS 1 gm3ro3

gm3ro3>>1 and ro3=ro4

1 Ad
A cm   CMRR   g m (ro 2 || ro 4 )2g m 3 R SS 
2 g m 3 R SS A cm

If ro2=ro4=ro : CMRR=(gmro)(gmRSS)
Bipolar differential pair with active load
Differential gain: it is obtained by calculation of Gm and Ro:

Sedra,6th edition,ISBN:9780199738519

v  v  If gm1=gm2=gm4=gm
vb3  g m1 id (re3 || ro3 || ro1 || r4 )  g m1re3  id  gm=(I/2)/VT
 2   2 
re3=1/gm
 v id  Gm=io/vid
vb4=vb3: g m4vb4   g m 4 g m1re 3  
 2  Gm= gm
 vid   vid   vid 
io  gm2    gm4 vb4 io  gm2    gm4gm1re3  
 2  2  2
Calculation of output resistance:
• Q1 and Q2 are common-base
• The input resistance of Q1 is being considered
as the emitter resistance of Q2.
• Input resistance of Q1: re1

R o 2  ro 2 [1  g m 2 ( re1 || r 2 )]  ro 2 (1  g m 2 re1 )  2 ro 2 Sedra,6th edition,ISBN:9780199738519

Current i is given by:

v v v v v vx
i x  x i x  2i  x  x  x Ro   ro 2 || ro 4
R o 2 2ro 2 ro 4 ro 2 ro 4 ix

vo
Ad   GmRo  gm(ro2 || ro4 )
vid
Differential gain
1
ro2  ro4  ro Ad  gmro
2
Input resistance: R id  2 r
Common-mode gain and CMRR
•REE is split to two resistors with the
Value of 2REE.
•Similar to calculations conducted
for MOSFET differential pair with the
active load:
ro4 2 ro4
Acm   
2R EE 3 3R EE

Ad   3 R EE 
 g m ( ro 2 || ro 4 )  
Sedra,6th edition,ISBN:9780199738519
CMRR  
A cm r
 o4 

For ro2=ro4=ro

1
CMRR   3 g m R EE
2
 Systematic input offset voltage
• It occurs due to the error in the current transfer ratio
(finite β value)
I
I C Q 1  I C Q 2 
2
Q4 and Q3 form a current source:
I4 1 I / 2
  I4 
I3 2 2
1 1
 PNP  PNP
I4 and I2 are not exactly matched values

I I / 2 I 2 /PNP I
i    
2 1 2 2 1 2 PNP
PNP PNP Sedra,6th edition,ISBN:9780199738519

To reduce ∆I to zero, an output voltage VOS is being applied at the input with the value of
i I /PNP 2VT
VOS    
Gm I / 2VT PNP