EXPERIMENT NO.

1
---------------------------------------------------------------------------------------------
OBJECTIVE: To characterize an n-channel MOSFET by measuring the device parameters

i. Channel length modulation coefficient (λ)

ii. Threshold voltage (Vt)
iii. Transconductance parameter (Kn)

SCHEMATIC:
i) For Vth and Kn:

V 1
0V dc

M 1

M b re a k N

ii) For λ

V1
0Vdc

M1
I

M b re a k N
V2
1 .7 V d c

THEORY:
Let VDS range from 0 - 3 V in 0.01V increments and let VGS range from 0 - 3V in 0.1V increments.
If gate is shorted to drain the saturation condition that is VDS> (VGS –Vt ) is always satisfied. In the
saturation mode, neglecting the channel length modulation, the drain current is described by,

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 Kn W 2
I D= (V GS −V t ) (1)
2 L

Now the square root of the drain current can be written as a linear function of gate to source voltage

Kn W
√ I D=
√ 2 L
(V GS−V t ) (2)

If the square root of measured drain current value is plotted against gate to source voltage it will be a
Kn W
linear curve. The slope of each curve is equal to
2 L√ . Thus the transconductance parameter Kn can

be simply calculated from this slope. The voltage axis intercept of the resulting curve can determined
the parameter Vto. By extrapolating the curves to zero drain current the threshold voltage Vt can be
computed. The voltage axis intercept of curve with Vsb = 0, gives the zero bias threshold volt.

The experimental measurement of the channel length modulation coefficient lambda requires a
different test circuit setup. The drain to source voltage is chosen sufficiently large (VDS>VGS-Vt) that
the transistor operation in saturation region. The saturation drain current is then measured for two
different drain voltages values VDS1, VDS2. Note that the drain current in the saturation mode is given by

Kn w 2
I D= ( V GS−V t ) ( 1+ λ V DS ) (3)
2 l

The ratio of ID1, ID2 is

I D 2 (1+ λ V DS 2)
= (4)
I D 1 (1+ λ V DS 1)

Which can be used to calculate the λ .This is in fact equivalent to calculating the slope of drain current
versus drain voltage curve in the saturation region. Print a plot of ID with VDS for different value of the
gate to source voltage VGS. Using this plot, parameter λ can be obtained.

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OUTPUT:

Fig: √ I D Vs Vgs

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 Fig: Id Vs Vds

RESULTS:

From curve 1, we find the threshold voltage to be V th = 0.7volts.

Using Equation 2 we find the value of the Tran conductance parameter by taking W= 160nm and
L=160nm. k n = 1.209mA/V.

Using equation 4 we find the value of channel length modulation coefficient to be λ = 0.1

4|Page
 EXPERIMENT NO. 2
---------------------------------------------------------------------------------------------
OBJECTIVE:
To study the voltage transfer-characteristics of CS Amplifier with

i. Passive load
ii. Diode connected NMOS and PMOS
iii. Current source Load
iv. Depletion load

THEORY:

1. Common-Source Stage with Resistive Load

Case 1: V ¿ <V TH
M 1 Is in cutoff region
∴ I D=0
∴ V 0 ut =V DD

Case 2: V TH <V ¿ <V 0 ut +V TH

M 1 Is in saturation region
∴ I D Increases with increase in V ¿

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∴ V 0 ut Decreases

Mid band small-signal gain is given by

∂V
A v = out
∂V¿
W
¿−RD μ n C ox ( V ¿ −V TH )
L

¿−gm R D

W
Since gmitself varies with the input signal according to gm =μn C ox ( V −V TH ), the gain of the circuit
L ¿
changes substantially if the signal is large. The dependence of the gain upon the signal level leads to
nonlinearity usually an undesirable effect. A key result here is that to minimize the nonlinearity, the
gain equation must be a weak function of signal-dependent parameters such as gm.

Case 3: V ¿ > ( V 0 ut +V TH )
M 1 enters into linear region.∴ V 0 ut further decreases but at slower rate.

R 1 V2

1k 5

M1
V1 V
1 .5 M b re a k n

CS with Resistive Load (DC model)

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OUTPUT (CS WITH RESISTIVE LOAD):

Fig: Vout Vs Vin Curve

AC RESPONSE:

CS with Resistive Load (AC model)

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OUTPUT:

10

-10

-20

-30
1.0Hz 10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz
DB(V(M1:d)/V(Vin:+))
Frequency

Fig 5: Gain Vs Frequency (in DB)

2. CS Stage with Diode-Connected Load

NMOS Load

M 2 is always in saturation

Case 1: V ¿ <V TH
M 1is in cutoff region

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∴ I D 1=0=I D 2

∴ V 0 ut =V DD−V TH 2

Case 2: V TH <V ¿ < ( V 0 ut +V TH )

M 1is in saturation region
∴ I D Increases with increase in V ¿
∴ V 0 ut Decreases
Mid band small-signal gain is given by
∂V out
A v=
∂V¿
g 1
¿− m1
g m2 1+η
( W /L )1 1
¿−
√ ( W /L )2 1+η

If the variation of ηwith the output voltage is neglected, the gain is independent of the bias currents and
voltages (so long as M 1stays in saturation). In other words, as the input and output signal levels vary,
the gain remains relatively constant, indicating that the input-output characteristic is relatively linear.

Case 3: V ¿ > ( V 0 ut +V TH )

As V ¿ exceeds ( V 0 ut +V TH ), M 1enters the triode region, and the characteristic becomes nonlinear.

M2 V2

5
M b re a k n

M1
V
V1
1 .5 M b re a k n

CS with Diode connected NMOS Load (DC model)

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OUTPUT:

5.0V

4.0V

3.0V

2.0V

1.0V

0V
0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V
V(M1:d)
V_V1

Fig 6 :Vout VsVin Curve

AC RESPONSE:

M2 Vdd
5

M b re a k n

C 1
M1
V
100p
V in
.2 5 M b re a k n
2 .5

CS with Diode connected NMOS Load (AC model)

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OUTPUT:

-0

-20

-40

-60

-80

-100
1.0Hz 10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz 1.0GHz
DB(V(M1:d)/ V(Vin:+))
Frequency

Fig 7: Gain Vs Frequency

PMOS Load

The circuit is free from body effect.

M 2is always in saturation

Case 1: V ¿ <V TH 1
M 1is in cutoff region
∴ I D 1=0=I D 2

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∴ V 0 ut =V DD−|V TH 2|

Case 2: V TH <V ¿ < ( V 0 ut +V TH 1 )

M 1 is in saturation region
∴ I D Increases with increase in V ¿
∴ V 0 utDecreases

Mid band small-signal gain is given by

∂V out
A v=
∂V¿
gm1
¿−
gm2
μ n ( W /L )1
¿−
√ μ p ( W / L )2

The gain of a common-source stage with diode connected load is a relatively weak function of the
device dimensions. The gain remains constant, indicating that the input-output characteristic is linear.

Case 3: V ¿ > ( V 0 ut +V TH 1 )

As V ¿exceeds ( V 0 ut +V TH 1 ) , M 1enters the triode region, and the characteristic becomes nonlinear.

M 2 Vdd

5
M b re a k p
V3

M 1 V
V1
1 .5 M b re a k n

CS with Diode connected PMOS Load (DC model)

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OUTPUT:
5.0V

4.0V

3.0V

2.0V

1.0V

0V
0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V
V(M1:d)
V_V1

Fig8 : Vout Vs Vin Curve

AC RESPONSE:

M2 Vdd

5Vdc
M b re a k p

C1

M1 V
100p
V in

0 .1 V a c M b re a k n
2 .5 V d c

CS with Diode connected PMOS Load (AC model)

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OUTPUT:
0

-10

-20

-30

-40

-50
1.0Hz 3.0Hz 10Hz 30Hz 100Hz 300Hz 1.0KHz 3.0KHz 10KHz 30KHz 100KHz 300KHz 1.0MHz 3.0MHz 10MHz
DB(V(M1:d)/V(Vin:+))
Frequency

Fig 9: Gain Vs Frequency

3. CS Stage with Current-Source Load

A more practical approach is to replace the load with a current source. Both transistors operate in
saturation. Since the total impedance seen at the output node is equal tor 01 ∥ r o 2, the gain is

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A v =−gm 1 ( r 01 ∥ r o 2 )

M3
V3
V2 5
2 .5 M b re a k n

M2
V
V1
1 .5 M b re a k n

CS with Current source NMOS Load (DC model)

OUTPUT:
2.5V

2.0V

1.5V

1.0V

0.5V

0V
0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V
V(M2:d)
V_V1

Fig 11: Vout Vs Vin

AC RESPONSE:

M 3 V dd

V 2 5V dc
3V dc M b re a k n

C 1
M 2 V
V 3 100p
0 .1 V a c
M b re a k n
2 .5 V d c

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 CS with Current source NMOS Load (AC model)

OUTPUT:
-10

-20

-30

-40

-50

-60

-70
1.0Hz 10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz
DB(V(M2:d)/V(V3:+))
Frequency

Fig12: Gain Vs Frequency

4. CS Stage with Depletion Load

Depletion mode NMOS is the form of digital logic Family that uses only a single power voltage. A
depletion mode load device with gate tighted with the drain is a much better load than an enhancement-
mode device, acting somewhere between a resistor and a current source.

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 V dd
M 2 5V dc

M 1
V
V 1
1 .5 V d c

CS with Depletion NMOS Load (DC model)

OUTPUT:
5.0V

4.0V

3.0V

2.0V

1.0V

0V
0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V
V(M1:d)
V_V1

Fig 13: Vout Vs Vin Curve

AC RESPONSE:

V2
M2 5Vdc

V
M1 C
100pf
0 .1 V a c V1
2 .5 V d c

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 CS with Depletion NMOS Load (AC model)

OUTPUT:

100mV

80mV

60mV

40mV

20mV

0V
10Hz 30Hz 100Hz 300Hz 1.0KHz 3.0KHz 10KHz 30KHz 100KHz 300KHz 1.0MHz 3.0MHz 10MHz 30MHz 100MHz
V(M1:d)
Frequency

Fig:14 Gain Vs Frequency

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 EXPERIMENT NO. 3
----------------------------------------------------------------------------------------------------------
OBJECTIVE: To study the voltage transfer characteristics and frequency response of

i. Common Gate Amplifier

ii. Common Drain Amplifier
iii. Cascode Amplifier

1. Common Gate Amplifier

A common-gate (CG) stage senses the input at the source and produces the output at the drain. The gate is
connected to a de voltage to establish proper operating conditions. Note that the bias current of M1 flows
through the input signal source.
For V ¿ ≥ V b−V TH , M1 is off and V out =V DD . For lower values of V ¿ M1 is in saturation. As V ¿
decreases, so does V out , eventually driving M1 into the triode region.
Small-signal gain:
∂V out
A v= =g m ( 1+η ) R D
∂V¿

SCHEMATIC DIAGRAM:

VD D
5Vdc

R 1
5k
0

Vout

M 1

M b re a k n
Vb
2Vdc
V in
0Vdc

0 0 0

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TRANSFER CHARACTERISTICS: V out vs V ¿

6
.
0
V

4
.
0
V

2
.
0
V

0
V0 0 1 1 2 2 3 3 4 4 5
VV . . . . . . . . . .
( 5 0 5 0 5V 0 5 0 5 0
R V V V V _
V V V V V V
1 V
: 3
1
)

Fig: Vout vs Vin

From the above figure, point A denotes output V out (max) =V DD =5 V at V ¿ =V b−V TH =1.3 V . For V ¿ below
point A, M1 is in saturation region. Point B denotes output V out (min) =V b−V TH =1.3 V at V ¿ =0.83 V . Between
point A and B, M1 is in Saturation region. For V ¿ below point B, M1 operates in linear region.

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FREQUENCY ANALYSIS:

SCHEMATIC DIAGRAM:

V D D
5 V d c

R 1
5 k
0

V o u t

M 1

M b re a k n
C L
V b 1 0 p
2 V d c
V in
5 0 m V a c
1 V d c

0 0 0 0

Gain vs Frequency:

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 6
.
4
8
4
5
76
.7
04
8
4
5
76
6.
45
8
4
5
76
6.
04
8
4
5
76
5. 1 1 1 1 1 1 1 1 1
54 0 D 0 . 0 0 . 0 0 .
8 H B 0 0 K F0 0 M 0 0
4 z ( H K H rK M H M G
5 V z H z eH H z H H
7 ( z qz z z z
5 M u
0 1 e
: n
d c
)/ y
V
(
V
3
:
+
)
)

2. Common Drain Amplifier

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 Analysis of the common-source stage indicates that, to achieve a high voltage gain with limited supply
voltage, the load impedance must be as large as possible. If such a stage is to drive a low-impedance load, then a
"buffer" must be placed after the amplifier so as to drive the load with negligible loss of the signal level. The
source follower (also called the "common-drain" stage) can operate as a voltage buffer.
The source follower senses the signal at the gate and drives the load at the source, allowing the source
potential to "follow" the gate voltage. Beginning with the large-signal behavior, we note that for V ¿ <V TH , M1
is off and V out =0. As V ¿ exceeds V TH , M1 turns on in saturation (for typical values of V DD) and I D 1 flows
through R S . As V ¿ increases further, V out follows the input with a difference (level shift) equal to V GS.
Small-signal gain:
∂V out g R
A v= = m S
∂ V ¿ 1+ gm RS

SCHEMATIC DIAGRAM:

VD D
5Vdc

0
M 1

M b re a k n
V in
0Vdc Vout

R s
10k

0 0
0

TRANSFER CHARACTERISTICS: V out vs V ¿

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 3
.
0
V

2
.
0
V

1
.
0
V

0
V0 0 1 1 2 2 3 3 4 4 5
VV . . . . . . . . . .
( 5 0 5 0 5V 0 5 0 5 0
R V V V V _V V V V V V
2 V
: 1
2
)

Fig :V out vs V ¿

From the above figure, point A denotes output V out (min) =7.1678 fV ≈ 0 V at V ¿ =V TH =0.7 V . After
point A M1 is in Saturation region. It will be evident from transfer characteristics that M1 does not enter the
triode region if V ¿ remains below V DD.

FREQUENCY ANALYSIS:

SCHEMATIC DIAGRAM:

VD D
5Vdc

0
M 1

M b re a k n

V in
50m Vac Vout
4 .5 V d c

R s C L
10k 10n

0 0 0 0

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Gain vs Frequency:

-
0

-
2
0

-
4
0

-
6
0

-
81 1 1 1 1 1 1 1 1
00 D 0 . 0 0 . 0 0 .
H B 0 0 K F0 0 M 0 0
z ( H K H rK M H M G
V z H z eH H z H H
( z qz z z z
M u
1 e
: n
s c
)/ y
V
(
V
3
:
+
)
)
From above figure, from Point A: Pass Band Gain: A v ( dB )=−1.3623 dB
From point B: 3 dB cut-off frequency = Bandwidth=36.671 KHz

3. Cascode Amplifier

25 | P a g e
 The cascade of a CS stage and a CG stage is called a "cascode" topology, providing many useful properties.
M1 generates a small-signal drain current proportional to V ¿ and M2 simply routes the current to R D. We call
M1 the input device and M2 the cascode device. Here M1 and M2 carry equal currents.
The minimum output level for which both transistors operate in saturation is equal to the overdrive
voltage of M1 plus that of M2. In other words, addition of M2 to the circuit reduces the output voltage swing by
at least the overdrive voltage of M2. We also say M2 is "stacked" on top of M1.
As V ¿ goes from zero to V DD, for V ¿ ≤ V TH 1, M1 and M2 are off, V out =V DD , and
V X ≈ V b −V TH 2 (if subthreshold conduction is neglected) .As V ¿ exceeds V TH 1, M1 begins to draw current, and
V out drops. Since I D 2 increases, V GS 2 must increase as well, causing V X to fall. As V ¿ assumes sufficiently
large values, two effects occur: (1) V X drops below V ¿ by V TH 1, forcing M1 into the triode region; (2) V out
drops below V b by V TH 2, driving M2 into the triode region. Depending on the device dimensions and the values
of R D and V b, one effect may occur before the other. For example, if V b is relatively low, M1 may enter the
triode region first. If M2 goes into deep triode region, V X and V out become nearly equal.
Small-signal gain:
∂V out
A v= =−g m 1 R D
∂V¿

SCHEMATIC DIAGRAM:

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 R s
10k
V out
V D D
M 2 5V dc

M b re a k n
V b
3V dc
0
M 1

M b re a k n
V in
0V dc

0 0
0 0

TRANSFER CHARACTERISTICS: V out vs V ¿

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 6
.
0
V

4
.
0
V

2
.
0
V

0
V0 0 1 1 2 2 3 3 4 4 5
VV V. . . . . . . . . .
( (5 0 5 0 5V 0 5 0 5 0
M MV V V V _V V V V V V
1 2 V
: : 3
d d
) )

From the above figure, point A denotes output V out (max) =V DD =5 V at V ¿ =V TH =0.7 V . For below point A,
both M1 and M2 turn on in saturation region as V ¿ ≥ V TH . As V b is relatively higher, M2 goes into linear region
first after point B and M1 remains in saturation region. Point B denotes output V out (mid)=V b −V TH 2 ≈ 2.3 V at
V ¿ =0.959 V . After point C, M2 also goes into Linear region. Point C denotes output V out (min) =0.552V at
V ¿ =1.0732V .

28 | P a g e
FREQUENCY ANALYSIS:

SCHEMATIC DIAGRAM:

R s
10k
V out
V D D
M 2 5V dc

M b re a k n
V b C L
3V dc 10p
0
M 1

M b re a k n
0
V in
10m V ac
0 .9 5 V d c

0 0 0
0

Gain vs Frequency:

From above figure, from Point A: Pass Band Gain: A v ( dB )=25.635 dB

From point B: 3 dB cut-off frequency = Bandwidth=404.212 KHz

29 | P a g e
 EXPERIMENT NO.4
---------------------------------------------------------------------------------------------
OBJECTIVE: To study following active resistors and compare their linearity
 MOS switch as an ac resistor
 Differential ac resistor
 Double Differential ac resistance

THEORY:
The ac resistor provides an ac voltage drop given an ac current. Ignoring the substrate terminal for the
moment, the MOS transistors are three-terminal devices. Through proper connection of these three
terminals, the active device becomes a two-terminal resistor called an active resistor.

1. MOS switch as an ac resistor:

When MOS transistor is in Triode region it acts as a voltage controlled resistor. The on
resistance is seen to consist of the series combination of R D, R S, and whatever channel resistance
exists. An expression for the on channel resistance can be found as follows. In the on state of the
switch, the voltage across the switch should be small, and V GS should be large. Therefore, the MOS
device is assumed to be in the ohmic region. Furthermore, let us assume that the channel length
modulation effects can be ignored. The drain current is given by

1 W
I D = K 'n [ 2 ( V GS−V T ) V DS−V DS2 ]
2 L

If V DS is less than V GS−V T but greater than zero. (V GSbecomes V GD if V DS is negative.) Assuming that
there is no offset voltage, the large signal channel resistance when V GS >V T is

1
r ac =RON =
W
K 'n ( V −V T −V DS )
L GS

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A lower value of RON is achieved for larger values of W /L

SCHEMATIC:

VD D
0Vdc

0
M1

M b re a k n
VG
0Vdc VB
5Vdc 0

OUTPUT:

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 1
3
m Vgs=8v Vgs=7v
A
1 Vgs=6v
0
m
A Vgs=5v

5 Vgs=4v
m Vgs=-2v
A
Vgs=3v

0
m
A

-
5
m
A

-
1
0
m
A
-
1
5
m
A
-
2 - - - - - - 0 0 1 1 2
0 2 I 1 1 0 0 0 . . . . .
m . D . . . . .V 4 8 2 6 0
A 0 ( 6 2 8 4 0_ V V V V V
V M V V V V VV
1 2
)

I D vs V DS

The above graph show the 1-V characteristics of MOS switch ac resistor using NMOS transistor
W 100 μ
with = and Level 1 Pspice model parameters. V DSis varied from -2 to 2V and V GS from 3 to
L 100 μ
8V

with V BS =−5 V . From the plot, it is observed that the linearity of this ac resistor is limited for
negative values of V DS by the effects of V BS and for positive values of V DS by V DS itself. The bulk
influences the linearity by causing V T to change. The drain-source voltage influences the linearity by
leaving the ohmic region and entering the saturation region. Techniques for eliminating both of these
effects are discussed in next active resistors.

32 | P a g e
 2. Differential ac resistor

Above figure shows a pair of ac resistors used in a differential configuration. In this case it is
possible to achieve an increase in linearity and to eventually even cancel the effects of V DS

1 W
I D = K 'n [ 2 ( V GS−V T ) V DS−V DS2 ]
2 L

W 1
∴ I 1=K 'n
L
( [
V C −V 2−V T ) ( V 1−V 2 ) − ( V 1−V 2 )2
2 ]
W 1
¿−I 2 =K 'n
L [( )]
V C +V 2−V T )( V 1+V 2) − ( V 1 +V 2 2
2

W
∴ I 1−I 2=K 'n ( V −V T ) 2 V 1
L C

2V 1
r ac =
I 1 −I 2

1
∴ r ac =
W
K 'n ( V −V T )
L C

Therefore, above circuit simulates a resistor r ac which is independent of V 1 or V 2as long as

|V 1−V 2|< ( V C−V T )

SCHEMATIC:

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 VD 1
2Vdc

M 1 M 2

M b re a k n M b re a k n

2V dc
V SS

VG G
5V dc 7V dc
V B
0

0 0

OUTPUT:
3
0
m
A

2
0
m
A

1
0
m
A

0
m
A

-
1
0
m
A
-
2
0
m
A
-
3 - - - - 0 0 1 1 2
0 2 I 1 1 0 V . . . .
m . ( . . . V 5 0 5 0
A 0 M 5 0 5 _ V V V V
V 1 V V V V
: 1
d
)
-
I
(
M
4
:
d
)

Fig: ( I D 1−I D 2 ) vs V D 1

34 | P a g e
 The above graph show the 1-V characteristics of Differential ac resistor using NMOS transistors
W 500 μ
with = and Level 1 Pspice model parameters. V 1=V D 1is varied from -2 to 2V and V C =V ¿
L 100 μ
from 3 to 8V with V BS =−5 V . The characteristics is considerably more linear than of MOS switch ac
resistor. For large values of V ¿, the linearity range increases. But this circuit cannot eliminate the effect
of bulk-source voltage

3. Double Differential ac resistor

A double-MOS, differential configuration, shown in above Figure, not only linearizes the ac
resistor but removes the influence of the bulk-source voltage. The relationship for the ac resistance can
be obtained by assuming all of the devices are matched and in the ohmic region.

W 1 W 1
∴ I 1=I D 1+ I D 3=K 'n
L
( [ 2 ]
V C1 −V 3−V T )( V 1−V 3 )− ( V 1 −V 3 )2 + K 'n
L
( [
V C 2−V 3 −V T ) ( V 2−V 3 ) − ( V 2−V 3 )2
2 ]
W 1 ' W 1
¿ I 2=I D 2 + I D 4=K 'n
L [ 2
] [
( V C2 −V 3−V T )( V 1−V 3 )− 2 ( V 1−V 3 ) + K n L ( V C 1−V 3 −V T ) ( V 2−V 3 ) − 2 ( V 2−V 3 )
2
]
W
∴ I 1−I 2=K 'n ( V −V C 2 ) ( V 1−V 2)
L C1

35 | P a g e
 W
∴ I 1−I 2=K 'n ( V −V T ) 2 V 1
L C

V 1−V 2
r ac =
I 1−I 2

1
∴ r ac =
W
K 'n ( V −V C2 )
L C1

Because all devices have been assumed to be in the ohmic region, above r ac equation only holds when

V 1 ,V 2 ≤ min [ ( V C 1−V T ) , ( V C 2−V T ) ]

SCHEMATIC:
Vc1

V3
0Vdc
M 1
M b re a k n
VB
Vc1

Vc1 M b re a k N M 2 0
7Vdc

VB
V1
2Vdc 5Vdc
VB
0 Vc2

0
Vc2

Vc2 M 3
0Vdc M b re a k N
VB

M 4

0
M b re a k N

Vc1

OUTPUT:

36 | P a g e
 ( I 1−I 2 ) vs V 1

The above graph show the 1-V characteristics of Double Differential ac resistor using NMOS
W 180 n
transistors with = and Level 1 Pspice model parameters. V 1is varied from -2 to 2V and V C 2
L 180 n
from 2 to 7V with V 1=−V 2, V 3=0V , V C 1=7 V and V BS =−5 V . Of all the realizations, the double
MOSFET differential resistor is superior in linearity.

However, the double-MOSFET differential resistor is really a trans resistance in that the voltages and
currents are at different terminals. This restricts the double-MOSFET differential resistance to trans
resistance applications that are found in differential-in, differential-out op amps. The parallel MOS
resistor and the single-MOSFET differential resistor are true resistor realizations that ·have
approximately the same linearity. However, the parallel MOS resistor is a true floating resistor
realization while the single MOSFET differential resistor must have a differential signal with reference
voltage VSS.

37 | P a g e
 EXPERIMENT NO. 5
---------------------------------------------------------------------------------------------
OBJECTIVE: To design and analyze the following current mirrors and compare their
performances in terms of output impedances and compliance voltages ( V omin ) .
 Simple Current Mirror
 Cascode Current Mirror
 Wilson Current Mirror

1. Simple Current Mirror

Schematic Diagram:
0

5Vdc 0Vdc
VD D Vout

Ire f
Io u t
R 1
1k

M 1 M 2

M b re a k n M b re a k N

Case 1:λ=0

38 | P a g e
 The structure consisting of M1 and M2 is called a "simple current mirror." In the general case, the
devices need not be identical. Neglecting channel-length modulation, we can write

Kn W K W
I REF = ( )
2 L 1
2
( V GS−V TH ) I out = n
2 L 2( )
( V GS −V TH )
2

Obtaining
W
I out =
L 2 ( )
I REF
W
L 1 ( )
The key property of this topology is that it allows precise copying of the current with no
dependence on process and temperature. The ratio of I out and I REF is given by the ratio of device
dimensions, a quantity that can be controlled with reasonable accuracy.

Current Copying Capability : I REF , I out vsV out

3
.
0
m
A (0.000,2.3345m) (1.8440,2.3345m)

2
.
0
m
A

1
.
0
m
A

0
A0 0 1 1 2 2 3 3 4 4 5
VI I . . . . . . . . . .
( D 5 0 5 0 5V 0 5 0 5 0
R ( V V V V _
V V V V V V
1 M V
) 2 2
)

39 | P a g e
 From the above graph, I out starts following I REF after Point A. Therefore compliance voltage is
given as V omin =1.8440 V and respective I out =I REF =2.334 mA

Case 2:λ ≠ 0

Channel length modulation effect results in significant error in copying currents. Current equations
can be rewritten as
K W K W
I REF = n ( )
2 L 1
2
( V GS−V TH ) (1+ λ V DS 1 )I out = n ( )
2 L 2
2
( V GS −V TH ) (1+ λ V DS 2)
Obtaining
W
I out =
( )
L 2 ( 1+ λ V DS 2 )
I REF
W ( 1+ λ V DS 1 )
( )
L 1

While V DS 1=V GS 1=constant , V DS 2, may not equal V GS 2and may vary because of the circuitry
fed by M2, which leads to varying I out in spite of constant I REF .

Current Copying Capability : I REF , I out vs V out

40 | P a g e
 6
.
0
m
A

4
.
0
m (0.000,2.7517m) (2.2520,2.7517m)
A

2
.
0
m
A

0
A0 0 1 1 2 2 3 3 4 4 5
VI I . . . . . . . . . .
( D 5 0 5 0 5V 0 5 0 5 0
R ( V V V V _V V V V V V
1 M V
) 2 2
)

By definition, compliance voltage is the minimum voltage required to keep M2 in saturation.

After Point A, M2 goes into saturation region. Therefore compliance voltage is given as
V omin =V GS 2−V TH =1.552V . Point B represents the point at which I out =I REF =2.7517 mA and respective
required output voltage is V out =2.2520V

Calculation of Rout : Consider I out vs V out graph

41 | P a g e
 5
.
0
m
A (3.9840,3.7575m
4 )
.
0 (2.8880,3.1223m
m )
A
3
.
0
m
A
2
.
0
m
A
1
.
0
m (0.000,0.000)
A
0
A0 0 1 1 2 2 3 3 4 4 5
VI . . . . . . . . . .
D 5 0 5 0 5V 0 5 0 5 0
( V V V V _V V V V V V
M V
2 2
)

For M2 in Saturation region, Rout can be calculated as

V out , B −V out , A
Rout =
I out , B −I out , A
3.9840−2.8880 V
Rout = =1.73 k Ω
3.7575−3.1223 mA

42 | P a g e
 2. Cascode Current Mirror

Schematic Diagram:
0

5 V d c 0 V d c
V D D V o u t

Ire f

R 1
1 k Io u t

M 3 M 4

M b re a k n M b re a k N

M 1 M 2

M b re a k n M b re a k N

Case 1:λ=0

Consider ( WL ) =( WL ) =( WL ) =( WL )
1 2 3 4
andV GS 1=V GS 2 (from the schematic diagram)
W W
But V GS 1=V GS 3 (as ( ) ( )
L 1
=
L 3
and I D 1 =I D 3=I REF )
W W
andV GS 2=V GS 4 (as ( ) ( )
L 2
=
L 4
and I D 2 =I D 4 =I out)

43 | P a g e
∴ V GS 1=V GS 3=V GS 3=V GS 4=V GS

M1, M2, M3 are always in saturation. When M4 goes into saturation by adjusting V out we can
write

Kn W K W
I REF = ( )
2 L 1
2
( V GS−V TH ) I out = n ( )
( V −V TH )
2 L 2 GS
2

Obtaining
I out =I REF

Current Copying Capability : I REF , I out vs V out

1
. (1.5240,871.698u)
0
m
A

0
.
5
m
A

0
A0 0 1 1 2 2 3 3 4 4 5
VI I . . . . . . . . . .
( D 5 0 5 0 5V 0 5 0 5 0
R ( V V V V _
V V V V V V
1 M V
) 4 2
)

From the above graph, I out starts following I REF after point A. Therefore compliance voltage is
given as V omin =1.5240 V and respective I out =I REF =0.871 mA

44 | P a g e
 Case 2:λ ≠ 0
Channel length modulation effect can be made independent of achieving current copying. Current
equations are
(1+ λ V DS 2)
I out = I
(1+ λ V DS 1) REF

(1+ λ V Y )
I out = I
(1+ λ V X ) REF
But V N =V GS 3 +V GS 1=V GS 4 +V DS 2
∴ V N =V GS 3 +V X =V GS 4 +V Y

But V GS 3=V GS 4
∴ V X =V Y
∴ I out =I REF

Current Copying Capability : I REF , I out vs V out

45 | P a g e
 1
.
5
m (0.000,1.1832m (3.4920,1.1832m
A ) )

1
.
0
m
A

0
.
5
m
A

0
A0 0 1 1 2 2 3 3 4 4 5
VI I . . . . . . . . . .
( D 5 0 5 0 V
5 0 5 0 5 0
R ( V V V V _
V V V V V V
1 M V
) 4 2
)

By definition, compliance voltage is the minimum voltage required to keep M4 in saturation.

After Point A, M4 goes into saturation region. Therefore compliance voltage is given as
V omin =2 V GS−V TH =2.792V and respective I out =I REF =1.1832mA

Calculation of Rout : Consider I out vs V out graph

46 | P a g e
 1
.
5
m (3.6840,1.1807m (4.4840,1.1980m
A ) )

1
.
0
m
A

0
.
5
m
A

0
A0 0 1 1 2 2 3 3 4 4 5
VI . . . . . . . . . .
D 5 0 5 0 5V 0 5 0 5 0
( V V V V _V V V V V V
M V
4 2
)

For M4 in Saturation region, Rout can be calculated as

V −V out , A
Rout = out , B
I out , B −I out , A
4.4840−3.6840 V
Rout = =46.24 k Ω
1.1980−1.1807 mA

Conclusions:

1. Compliance Voltages: V omin

( V omin )Simple < ( V omin )Cascode < ( V omin )Wilson

2. Output Resistance: Rout

( Rout ) Simple < ( R out )Wilson < ( R out )Cascode

47 | P a g e
 3. Wilson Current Mirror

Schematic Diagram:
0

5V dc 0V dc
VD D Vout

R 1
1k Io u t

I re f
M 3

M b re a k n

M 1 M 2

M b re a k n M b re a k N

Case 1: λ=0

Consider ( WL ) =( WL ) =( WL ) and V =V
1 2 3
GS 1 GS 2 (from the schematic diagram)

W W
But V GS 2 =V (as ( ) =( ) and I =I =I
GS 3 D2 D3 out )
L L 2 3

∴ V GS 1=V GS 2=V GS 3=V GS

M1, M2 are always in saturation. When M3 goes into saturation by adjusting V out we can write

Kn W K W
I REF =
2 L 1 ( ) 2
( V GS−V TH ) I out = n
2 L 2
( V GS −V TH )
2
( )
Obtaining
I out =I REF

48 | P a g e
Current Copying Capability : I REF , I out vs V out

1.0mA

0.5mA

0A
0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V
ID(M3) ID(M5)
V_Vout
From the above graph, I out starts following I REF after point A. Therefore compliance voltage is given as
V omin =3.00 V and respective I out =I REF =0.9275 mA

Case 2: λ ≠ 0
Channel length modulation effect results in systematic error in copying currents. Current equations can be
rewritten as. Current equations are
(1+ λ V DS 2)
I out = I
(1+ λ V DS 1) REF

But V DS 1=V GS 3 +V GS 2=2 V GS

And V DS 2=V GS 2=V GS

49 | P a g e
 (1+ λ V GS)
∴ I out = I
(1+2 λ V GS ) REF

∴ I out < I REF (Always)

Current Copying Capability : I REF , I out vs V out

1.5mA

(3.7951,966.343u) (4.4016,985.952u)
1.0mA

0.5mA

0A
0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V
ID(M3) ID(M5)
V_Vout
Theoretical analysis results in 4th degree polynomial so cannot be verified with the graphical results.

Calculation of Rout : Consider above I out vs V out graph

V out , B −V out , A
For M3 in Saturation region, Rout can be calculated as Rout =
I out , B −I out , A
4.4016−3.7951 V
Rout = =30.943 kΩ
0.9859−0.9663 mA

Conclusions: 1. Compliance Voltages: V omin

( V omin )Simple < ( V omin )Cascode < ( V omin )Wilson
2. Output Resistance: Rout

( Rout ) Simple < ( R out )Wilson < ( R out )Cascode

50 | P a g e
 EXPERIMENT NO. 6
--------------------------------------------------------------------------------------------
OBJECTIVE: To study DC and frequency response of CMOS OTA.

THEORY:

BASIC OPERATION:
The operational trans-conductance amplifier (OTA) is an amplifier whose differential input voltage
produces an output current and hence it is a voltage controlled current source (VCCS). There is usually
an additional input for a current to control the amplifier's trans-conductance. The OTA is similar to a
standard Operational Amplifier in that it has a high impedance differential input stage and it may be
used with negative feedback. Opamp is used to drive loads which are resistive or capacitive; whereas
OTAs are used to drive purely capacitive loads (small cap. loads).
In the ideal OTA, the output current is a linear function of the differential input voltage, calculated as
follows:

where Vin+ is the voltage at the non-inverting input, Vin− is the voltage at the inverting input and gm
is the transconductance of the amplifier. The amplifier's output voltage is the product of its output
current and its load resistance: =

(ii) The voltage gain is then the output voltage divided by the differential input voltage: =

(iii) The Transconductance of the amplifier is usually controlled by an input current, denoted as Itune
or Iabc ("amplifier bias current"). The amplifier's transconductance is directly proportional to this
current. This is the feature that makes it useful for electronic control of amplifier gain. CMOS
technologies are very convenient for implementing OTAs because their MOSFETs are inherently
voltage-controlled current devices. A variety of CMOS OTAs with different topologies have been
developed for different purposes so far. According to their input/output topologies, they can be
categorized into three types, i.e., single input/output, differential-input single-output, and differential
input/output.

51 | P a g e
Fig indicates Differential I/O topology of OTA. In this topology, two current mirrors are used to
improve balance between differential paths. The current mirrors have size ratio B to boost output
current by B- Comparative Analysis of CMOS OTA www.iosrjournals.org 4 | Page times. As vi+
increases it results in increase in value of id+, which is transferred to output side with B-times
multiplication. Similarly, the change in id-, due to current mirror on right side it gets B-times as
compare to id

SCHEMATIC:

M b re a k P M b re a k P
M b re a k P M b re a k P V3
2 .5 V d c
M 8 M 5
M6 M 7

I1 M 1 M2

50uAdc
M b re a k N M b re a k N
V4
0Vdc

0 0
0V

M 3 M9 M4

M b re a k N M b re a k N M b re a k N

V1
-2 .5 V d c

52 | P a g e
For above schematic, the following parameters are used:

L=0.72 u for all transistors.

For M3, M9 and M4: W=1.44 u

For M1 and M2: W=2.16 u
For M5, M6, M7, M8: W=5.76 u

OUTPUT:

0
A
(-208.333m,-17.978n)

-
5
u
A

(195.513m,-9.736u)

-
1 - - - - 0 0 1 1 2
0 2 I 1 1 0 V . . . .
u . D . . . V 5 0 5 0
A 0 ( 5 0 5 _ V V V V
V M V V V V
7 4
)

53 | P a g e