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vGS ≥ VT vGS ≥ VT
VGS < VT
vDS < vGS –VT vDS ≥ vGS –VT
5.0
1 W
Kn = μnCox vGS = 5 V
2 L 4.0
drain current — iDS (mA)
3.0
3-terminal D
vGS = 4 V
symbol iD 2.0
+
vDS vGS = 3 V
G + 1.0
vGS – vGS = 2 V
– 0.0 vGS < VT
S 0.0 2.0 4.0 6.0 8.0 10.0
drain voltage — vDS (V)
G. Tuttle - 2022 NMOS examples – 1
Example 1
RD iD
For the circuit shown, use the the 1.0 kΩ
NMOS equations to nd iD and vDS. +
vDS + V
+ – DD
vGS – 15 V
For the NMOS, VT = 1 V VGG + –
and Kn = 0.5 mA/V2. –
5V
We see that
vGS = VGG = 5 V > VT → the NMOS is on.
Guess that the transistor is in saturation.
iD = Kn (vGS − VT)
2
To help decide the issue, we could guess that the transistor is off,
meaning that we are assuming vGS < VT. However, if the NMOS is off,
then iD = 0. This makes vGS = VGG – iDRS = VGG = 5 V. This is greater than
VT, meaning that the transistor should be on — in exact contradiction to
the assumption of the transistor being off. So the transistor must be on.
Next, is the NMOS in saturation or ohmic? Here we can’t even make a
logical argument as we did in deciding on or off. So we must guess —
let’s guess saturation and see what happens.
G. Tuttle - 2022 NMOS examples – 3
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Example 2 (cont.)
If the transistor is in saturation
iD = Kn (vGS − VT) .
2
Also, we know that vGS = VGG – iDRS. Inserting into the saturation current
equation:
iD = Kn (VGG − iD RS − VT)
2
( ) KnRS2 ( )
VGG − VT 1 VGG − VT
iD2 − 2 + iD + =0
RS RS
G. Tuttle - 2022 NMOS examples – 4
Example 2 (cont.)
Now, using our old-fashioned calculator (Or slide rule. Or abacus. Or
ngers and toes.), we can plug in the numbers.
2
2 2 ax + bx + c = 0
iD − (10 mA) iD + 16 mA = 0.
b ± b 2 − 4ac
(Note the units on the third term.) x=−
2a
Use the quadratic formula to nd If a = 1:
(2)
2
b b
iD = 2 mA or iD = 8 mA. x=− ± −c
2
So another conundrum: Which is it? Or both?
The correct solution must be consistent with the NMOS being on and in
saturation. Only one root will meet both conditions. Start with
iD = 8 mA. In that case, vGS = VGG – iDRS = 5 V – (8 mA)(1kΩ) = –3 V. This
is (a lot) less thanVT. The larger root fails the “on” test rather badly.
Now consider iD = 2 mA. In that case, vGS = 3 V > VT. So the NMOS is
clearly on. Next, vDS = VDD – iDRD – iDRS = 15 V – 2 V – 2 V = 11 V,
which is clearly bigger than vGS – VT = 2 V. The saturation assumption is
also con rmed. So the correct answers are:
G. Tuttle - 2022
iD = 2 mA and vDS = 11 V. NMOS examples – 5
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Example 3 VDD
iG = 0 15 V
For the circuit shown, nd iD and vDS. Calculate the
power being dissipated in the NMOS and the resistor. iD
+
For the NMOS, VT = 1 V and Kn = 0.5 mA/V2. vDS
+ –
We start by noting that the gate is tied to the drain — the vGS
NMOS is now essentially a term-terminal device. As –
always, there is no current owing into the gate. Given the RS
connections, is obvious that vGS = vDS. This means that the 1 kΩ
NMOS can either be off or in saturation. It cannot be in
the ohmic mode of operation — with gate tied to drain,
vDS is always bigger than vGS – VT.
Then, by the same argument used in Example 2, we know
that the NMOS must be on. If the NMOS must be on and it
can’t be in ohmic, then it must be operating in saturation:
iD = Kn (vGS − VT)
2
and
vGS = VDD − iD RS.
G. Tuttle - 2022 NMOS examples – 6
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Example 3 (cont.)
Putting the two equations together,
iD = Kn (VDD − iD RS − VT)
2
( ) KnRS2 ( )
VDD − VT 1 VDD − VT
iD2 − 2 + iD + = 0.
RS RS
Plugging in numbers:
iD2 − (30 mA) iD + 196 mA2 = 0.
Using the quadratic equation to nd the two roots:
iD = 9.61 mA or iD = 20.39 mA.
[ KnRD ] KnRD
1 VDD
2
vDS − 2 (vGS − VT) + + =0
G. Tuttle - 2022 NMOS examples – 10
Example 4 (con’t)
Plugging in the values:
2
vDS − [8.2 V] vDS + 3 V2 = 0
(Again, note units on the third term.) Use the quadratic formula to nd
the roots:
vDS = 0.384 V or vDS = 7.82 V.
Once again, we must determine which of these is consistent with the
transistor being in ohmic, meaning that the root should be less than
vGS – VT = 4 V. The larger root is clearly too big. The smaller root works,
so the correct answer is vDS = 0.384 V. Then
VDD − vDS 15 V − 0.384 V
iD = = = 1.46 mA
RD 10 kΩ
So the corrects answers are:
iD = 1.46 mA and vDS = 0.384 V.
Obviously, changing RD had a big effect on the transistor’s mode of
operation.
G. Tuttle - 2022 NMOS examples – 11
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Example 5 VDD
For the circuit shown, nd iD , vDS, and calculate the 5V
RD iD
power being dissipated in the NMOS and resistor for 1 kΩ
VGG = 0.5 V, VGG = 2.5 V, and VGG = 5 V. +
VGG vDS
For the NMOS, VT = 1 V and Kn = 0.5 mA/V2. + –
vGS
Again, this looks very much like Example 1, –
with different applied voltages. Consider each in turn.
In all cases, vDS = VDD – iDRD. In each case, we must nd either iD or vDS,
and then other quantity is easily calculated.
VGG = 0.5 V:
vGS = VGG = 0.5 V < VT !! → the NMOS is off, and the current must be
zero.
iD = 0 → vDS = VDD = 5 V.
With iD = 0, there is no power dissipated in either the transistor or the
resistor.
Then
vDS = VDD − iD RD = 5 V − (1.125 mA) (1 kΩ) = 3.875 V
Check:
vGS − VT = 1.5 V
vDS > vGS – VT → saturation con rmed.
PNMOS = vDS · iD = (3.875 V)(1.125 mA) = 4.36 mW
PRS = iD2·RD = 1.27 mW.
Then
vDS = VDD − iD RD = 5 V − (8 mA) (1 kΩ) = − 3 V
Urk. Suspicion con rmed. It’s not saturation so it must be ohmic. (See
Example 4.)
iD = Kn (vGS − VT) ,
2
As seen in previous examples, vGS = VTh – iDRS. Inserting into the current
equation gives the expected quadratic equation:
iD = Kn (VTh − iD RS − VT) ,
2
( RS ) KnRS2 ( RS )
VTh − VT 1 VTh − VT
iD2 − 2 + iD + =0
Yikes! This looks very unpleasant. Plug into a solver. Or do the algebra (Urk):
[ ]
Kn
iD2 + iD + =0
RS2 − RD2 RS2 − RD2
(Note that we must be careful if RS = RD. But, if they are equal, it is no longer a
quadratic — the math is actually a bit easier.) Now plug in numbers:
iD2 − (0.7539 mA) iD − 1.4225 mA2 = 0 → iD = 1.63 mA or iD = − 0.874 mA
The negative value is not possible, so the correct current is 1.63 mA.
Then vDS = VDD − iD (RD + RS) = 0.721 V and vGS = VTh − iD RS = 6.87 V.
We see that vDS < vGS – VT, consistent with the NMOS in ohmic. Whew!
G. Tuttle - 2022 NMOS examples – 19
Example 7
Design the circuit at right (by choosing Kn for VDD
the NMOS and the value of RS) so that iD = 1 mA iD 5V
+
and vDS = 2.5 V. The NMOS has VT = 1 V. VGG vDS
+ –
By writing a loop equation around the drain- 4V vGS
source loop, we see that vRS = VDD – vDS = 2.5 V. –
And so the value of should be RS
RS = (2.5 V)/(1 mA) = 2.5 kΩ.
Now writing a loop equation around the gate-
source loop, we see that
vGS = VGG – vRS = 4 V – 2.5 V = 1.5 V.
Since vDS = 2.5 V, having vGS = 1.5 V means that
the NMOS will be operating in saturation.
iD 1 mA mA
Kn = = =4 2
(vGS − VT) (1.5 V − 1.5 V)
2 2 V
G. Tuttle - 2022 NMOS examples – 20
Example 8
VDD
Design the circuit at right (by choosing Kn for the 10 V
NMOS and the value of RD) so that iD = 10 mA and RD iD
vDS = 0.2 V. The NMOS has VT = 1 V. How much
power is being dissipated in the resistor and the +
VGG vDS
NMOS? +
5V vGS –
Using KVL, if vDS = 0.2 V, then vRD = 9.8 V. –
For a current of 10 mA,
RD = vRD / iD = (9.8 V)/(10mA) = 0.98 kΩ.
iD 10 mA mA
Kn = = = 6.41
2 (vGS − VT) vDS − vDS
2 2 (5 V − 1 V) (0.2 V) − (0.2 V)2 V2
V
The same current ows in M1, which we know must be in saturation.
With vGS1 = vDS1, we can write
iD = Kn1 (vGS1 − VT) = Kn1 (vDS1 − VT)
2 2
iD 1.6 mA
vDS1 = VT ± = 1V ± = 1V ± 4V
Kn1 0.1
mA
V2
We have solved that one before (see Example 2), either directly with a
calculator or with some familiar algebra:
2
( ) Kn2 RS2 ( )
VGG2 − VT 1 VGG2 − VT
iD2 − 2 + iD + =0
RS RS