2.

MOS: Transfer Function, Bias, and

Small Signal Model
Reading: Sedra & Smith: Secs. 5.4 & 5.5
(Also see Sec. 4.3.7)

ECE 102, Winter 2011, F. Najmabadi

NMOS Characteristic Equations

PMOS

For PMOS: vGS vSG, vDS vSD, vtn |vtp|, kn kp, and iD flowing OUT of the drain

NMOS Transfer Function

For vGS < Vtn , NMOS is in cutoff:

NMOS Transfer Function

o For vGS > Vtn

as

vGS

iD

vDS

o (NMOS in saturation as we started with vDS = VDD > vGS Vtn )

o iD and vDS can be found from

NMOS Transfer Function

o As vGS increases vDS becomes smaller until at point B where vDS = vGS Vtn .
o For larger vGS NMOS is in triode
Exercise: Find VGS|B and VDS|B

NMOS Transfer Function

A combination of constant VGS and a signal (vgs)

Bias

Bias

A combination of constant VGS and a signal (vgs)

Bias and signal

Bias

Bias and signal

Response to the signal appears to be linear!

Bias and signal

A linear transfer function for the Signal!

vds
Signal and
response
vGS = VGS + vgs
vDS = VDS + vds
iD = IDS + id
Bias

vgs

An Analogy
Response
hb

Added Weight
(signal)

Boat
Hb = HB

Pool
Bias

HB

Hb

Bias + signal

Total Height, Hb = Bias (HB) + response to signal (hb)

Complicated correlation between total height, Hb , and weight
of the boat.
Simple correlation between hb and added weight

hb

Added Weight
(signal)

HB

Hb

Bias + signal

Bias: HB
Bias + Signal: Hb
Signal &
response to signal: hb

Bias: VGS , VDS , ID , VRD

Bias + Signal: vGS , vDS , iD , vRD
Signal &
response to signal: vgs , vds , id , vrd

Non-linear correlations among Bias + Signal: vGS , vDS , iD , vRD

Simple (and linear) correlation between signal and response to the
signal: vgs , vds , id , vrd

Important Points!
Signal: We want the response of the circuit to this input.
Bias: State of the system when there is no signal (current and
voltages in all elements).
o Bias is constant in time (may vary extremely slowly compared to
signal)
o Purpose of the bias is to ensure that MOS is in saturation at all times.

Response of the circuit and elements within to the signal is

different that the response of the circuit and its elements to
Bias (or to Bias + signal):
o Different transfer function for the circuit
o Different iv characteristics for the elements, i.e. relationships among
vgs , vds , id is different than relationships among vGS , vDS , iD .

Limitations and Constraints

Floating Boat analogy
Boat should float at all
times!
o Sufficient water in the pool

Transistor
MOS should be in saturation
at all times!
o Bias point in Saturation*
VGS > Vtn
VDS > VGS - Vtn

o Cannot put too much weight

(depends on the depth of the
water!)

o Signal amplitude cannot

become too large (depends
on Bias point!)*
vGS = VGS + vgs > Vtn
vDS = VDS + vds > VGS + vgs- Vtn

* Equations are for NMOS!

Procedure:
1. How to establish a Bias point (bias is the state of the
system when there is no signal).
o

Stable and robust bias point should be resilient to variations in k,

Vt , due to temperature and/or manufacturing variability.

2. Find the iv characteristics of the elements for the signal

(which can be different than their characteristics equation
for bias).
o

This will lead to different circuit configurations for bias versus

signal

3. Compute circuit response to the signal

o

Focus on fundamental MOS amplifier configurations

BIAS

(Ensure that MOS is in saturation at all times,

Important parameters are ID and VDS )

Bias with Gate Voltage

ID = 0.5 kn (W/L) (VGS Vtn)2

VDS = VDD RD ID

This method is NOT desirable as k, Vt , are not well-defined

as bias point (i.e., ID and VDS) can change due to temperature
and/or manufacturing variability.
o See Exercise 5.33

Bias with Source Degeneration

Basic Arrangement

VGS = VG RS ID

Bias with one power supply

Bias with two power supplies

VGS = VG RS ID

VGS = VSS RS ID

(KVL: 0+ VGS + RS ID VSS = 0)

Resistor Rs provides negative feedback

Resistor Rs provides negative feedback

VGS = VG RS ID
ID = IS = 0.5 kn (W/L) (VGS Vtn)2

Negative Feedback:
o If ID (because kn or Vtn )
o If ID (because kn or Vtn )

Basic Arrangement
VGS Eq.
VGS Eq.

VGS
VGS

ID Eq.
ID Eq.

ID
ID

Feedback is most effective if RS ID >> VGS as

0 = VGS + VG RS ID VG RS ID

or ID VG /RS

Example: Find Bias point for Vt =1 V, k W/L = 1 mA/V2

VG = (7)/(7+8) X 15 = 7 V
GS-KVL: VG = VGS + RS ID
VG = 7 V

VD = 10 V

ID = 0.5 kn (W/L) (VGS Vtn)2

VS = 5 V

VGS = 2 V , VS = VG VGS = 5 V

7 = VGS + 5 (VGS 1)2

DS-KVL: 15 = VDS + (RS + RS )ID

VDS = 5 V , VD = VS + VDS = 10 V

Impact of RS:
if Vt = 1.5 V (50% change), ID = 0.455mA (9% change)

Bias in ICs
Resistors take too much space on the chip
A robust bias has ID and VDS that do not change. One can
force ID to be constant using a current source.
ID = I

VG = 0

VD = VDD RD ID
VGS is set by
I = ID = 0.5 kn (W/L) (VGS Vtn)2
VS = VG VGS = VGS
VDS = VD VS

Current Mirrors (or Current Steering Circuits)

Identical MOS:
Same kn and Vt

Since VGS1 = VGS2 = VGS :

Circuit works as long as Q2 is in saturation

VDS2 > VGS - Vt
Q1 is always in saturation
VDS1 = VGS > VGS - Vt

An implementation of a Current Mirror

Identical MOS:
Same kn and Vt

Bias point of Q1 is uniquely set by:

Since VGS1 = VGS2 = VGS :

Circuit works as long as Q2 is in saturation

VDS2 > VGS - Vt

Examples of Current Steering circuits

Current steering circuit can bias several transistors

A PMOS current mirror

An implementation of current steering

circuit to bias several transistors in an IC

SMALL SIGNAL MODEL

2.

Find the iv characteristics of the elements for the signal (which can be
different than their characteristics equation for bias).
This will lead to different circuit configurations for bias versus signal

Signal-only circuit is different!

Bias
VDD: VDD
R D:

VRD
IRD = ID

Signal only

MOS: VGS, ID, VDS

Bias and signal

No signal here!
VDD: VDD
RD:

vRD = VRD + vrd

iRD = iD = ID + id

MOS: vGS = VGS + vgs

vDS = VDS + vds
iD = ID + id

RD:

vrd
ird = id

MOS: vgs, id, vds

Signal Model for linear circuit elements

Independent voltage source (e.g., VDD)
o No signal: effectively grounded

Independent current source

o No signal: effectively open circuit (Careful about current mirrors as they
are NOT ideal current sources, channel width modulation was ignored!)

Resistors, capacitors, inductor

o Remain the same:

Dependent sources

iR =
vR =
vR =
vR =
vr =

IR + ir
VR + vr = RIR + vr
R iR = R (IR + ir ) = RIR + R ir
RIR + vr = RIR + R ir
R ir

o Remain the same with the control parameter related to the signal!

Non-linear Elements:
o Different!

Diodes: signal response is non linear but can be

linearized when signal is small
vD
iD

vd

VD
ID

id

vd
id

R = nVT/ID

Formal derivation of small signal model

XA
x A = X A + xa

YA = f ( X A )
y A = f ( xA )

xA

f()

YA

f()

y A = YA + y a

g()

yA

( 2)
f
(X A)
2
(1)
= f ( X A ) + f ( X A ) (x A X A ) +
( x A X A ) + ...
2!
( 2)
f (X A) 2
(1)
= f ( X A ) + f ( X A ) xa +
xa + ...
2!
f ( X A ) + f (1) ( X A ) xa
Small signal means:
( 2)
f
(X A) 2
(1)
(1)
f ( X A ) xa >>
xa
y a = g ( xa ) = f ( X A ) xa
2!

f (1) ( X A )
xa << 2 ( 2 )
f (X A)

Derivation of diode small signal model

nVvD

iD = I S e 1

VD
nV

I D = f (VD ) = I S e T 1

nV
IS e T
(1)
id = f (VD ) vd =
nVT

nVx
f ( x) = I S e T 1

VD

nV
IS e T

vd =

nVT

x =VD

ID + IS

vd = nV vd
T

ID
ID + IS
id =
vd
vd
nVT
nVT

vd
id =
rD

nVT
rD
ID

vd
id

R = nVT/ID

Derivation of MOS small signal model

x A = X A + xa

xA
yA

y A = YA + y a
z A = f ( xA , y A )

XA

Z A = f ( X A , YA )

YA

f(, )

zA

f(, )

ZA

za = z A Z A
z A = f ( xA , y A )

= f ( X A , YA ) +

f ( x, y )
x

f ( x, y )
ZA +
x

( xA X A ) +
X A ,YA

f ( x, y )
xa +
y
X A ,YA

f
za =
x

f
xa +
y
X A ,YA

f ( x, y )
y

ya
X A ,YA

ya
X A ,YA

( y A YA ) + ...
X A ,YA

Derivation of MOS small signal model

iG = 0
iD = 0.5 kn (W/L) (vGS Vtn)2 (1 + vDS) = f (vGS , vDS)
iD = f (x, y)

with x vGS and y vDS

f
f
vds
id =
v gs +
x VGS ,VDS
y VGS ,VDS

id = g m v gs +
ig = 0

vds
ro

gm =

ro =

2 ID
VGS Vtn

1
ID

For vDS << 1

MOS circuit small signal model

id = g m v gs +

2 ID
gm =
VGS Vtn

vds
ro

1
ro =
ID

and ig = 0
id

2
>> 1
g m ro =
(VGS Vtn )

PMOS circuit model for small signals is identical to NMOS

in gm formula replace VGS Vtn with VSG - |Vtp|

PMOS circuit small signal model is identical to NMOS

vsd
id = g m vsg +
ro

vsg

2 ID
gm =
VSG Vtp

and ig = 0
id

gmvsg

id

1
ro =
ID

For PMOS small signal model, id flows into the drain