JFET BIASING

4 types of biasing circuit will be studied in this course:

(i). Fixed biasing

(ii). Self biasing
(iii). Mid-point biasing
(iv). Voltage division biasing

Before analyzing the respective biasing circuitries, Q

point and load line need to be known.

1. Load line and Q-point

A load line connects 2 points on the drain
characteristic. One point is on the ID axis and the
other is on the VDS axis. For a known VGS, the
intercept point between the load line and the drain
curve can determine the operating/quiescent (Q) point
and consequently, the IDQ and VDSQ.

ID Load line (determined

from the circuit)

IDSS VGS =0
-1V
Q-point
IDQ -2 V( VGSQ )
-3 V
-4 V
VDS(sat) = Vp VDSQ VDS VGS(off)

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2. Fixed biasing

RD
ID VDD
RG
VDS
VGG
ID

To determine the Q-point (IDQ and VDSQ), the

relationship between the ID and VDS needs to be
known.

Looking at the output loop (Loop 1 - drain

characteristic):

-VDD +IDRD +VDS =0

ID = VDD - VDS =- 1 VDS + VDD
RD RD RD

This expression is in the form of y = mx + c.

Slope is - 1 and c = VDD .

RD RD

If ID = 0, VDS = VDD. Hence, the load line intersects the

ID axis at VDD and the VDS axis at VDD.
RD

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Slope is - 1 and c = VDD . At ID = 0, VDS = VDD.
RD RD
Hence, the load line intersects the ID axis at VDD and
RD
the VDS axis at VDD. Once VGSQ is known, IDQ and VDSQ
can be determined.

ID
Load line with
VDD
a slope of - 1
RD RD
IDSS VGS =0
VGS1
Q-point
IDQ VGSQ
VGS2
VGS3
Vp VDSQ VDD VDS VGS(off)

3. Self-biasing

In order to operate in the saturation region (hence, as

an amplifier), G-S of the JFET needs to be reverse
biased. To obtain this condition, the VGS has to be
negative for the n-channel JFET and positive for the
p-channel JFET. The following topologies will enable
the mentioned condition to be achieved without the
need of an external voltage to be connected to the G.
Due to this capability, this topology is called self-
biasing circuit.

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 RD RD
ID VDD ID VDD
VDS VSD
ID ID
RG RG
RS RS

In Cct. A:
-VDD + IDRD + VDS + IDRS = 0.
IDRD + VDS + IDRS = VDD.
VS = IDRS is positive.
Since IG ≈ 0, then VRG ≈ 0. Hence, VG = 0.
Since VG = 0 and VS is positive, VGS=VG-VS= negative.
So, the n-channel is properly biased as an amplifier.
VGS= -VS = - IDRS.
RS = VS / ID.

In Cct. B:
IDRS + VSD + IDRD - VDD = 0.
IDRS + VSD + IDRD = VDD.
Since IDRS is positive and 0 - VS = IDRS , VS = - IDRS.
Therefore, VS is negative.
Since IG ≈ 0, then VRG ≈ 0. Hence, VG = 0.
Since VG = 0 and VS is negative, VGS=VG-VS= positive.
So, the p-channel is properly biased as an amplifier.
VGS= -VS = IDRS.
RS = VGS / ID.

For both n- and p-channel JFET, RS = |VGS| / ID.

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 RD RD
ID VDD ID VDD
VDS VSD
ID ID
RG RG
RS RS

In the JFET, majority carriers are moving from S to D.

In the n-channel JFET, VDD is positive to attract the

electrons to move from S to D. Conventional current
flow is opposite to the flow of electron. Hence, the
direction of current is from D to S.

In the p-channel JFET, VDD is negative to attract the

holes to move from S to D. Conventional current flow
is the same as the flow of holes. Hence, the direction
of current is from S to D.

Determining the operational point of the self-biasing

JFET

2 ways:

1. graphical method, i.e. from the transfer and drain

characteristic
  2
2. from calculation, i.e. using ID =I 
DSS 1- VGS 
 VGS(off) 

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Example 1

Determine the RS that is needed to self bias an n-

channel JFET that has the transfer characteristic
curve as shown below at VGS = -5 V.

ID (mA)

IDSS RD
ID VDD
VDS
ID
RG
RS

-VGS(V)
VGS(off)

Solution

From the graph, at VGS = -5 V, ID = 6.25 mA.

RS = |VGS | / ID = 5 / 6.25 m = 800 Ω

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Example 2

Determine VDS and VGS. Given ID = 5 mA.

10 V

RD =1kΩ
D ID
G +V
- DS
RG S ID
RS =500 Ω

Solution:

VG = 0 V (criteria of the self-biased circuit).

VS = IDRS = 5m x 500 = 2.5 V
VGS = - VS
VGS = -2.5 V
VDD = IDRD + VDS + IDRS
VRD = IDRD = 5m x 1k = 5 V
VRS = IDRS = VS = 2.5 V
VDS = 10 – 5 – 2.5 = 2.5 V

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4. Mid-point biasing

The JFET is typically biased near the mid-point of the

drain characteristic curve to achieve maximum signal
swing at the input. The purpose is to obtain maximum
undistorted ouput signal.
ID

IDSS VGS =0
-1V
IDQ VGSQ
-4 V
Vp VDSQ VDS

Steps to obtain the Q-point

1. Mid-point biasing enables maximum drain current

swing between IDSS and 0. Hence, IDQ = IDSS .
2
  2
2. From ID =I 1- V GSQ  and when IDQ = IDSS ,
DSS 

VGS(off)  2
VGS(off)
VGSQ ≈ .
3.4
3. To set the drain voltage at mid-point, VD = VDD .
2
4. Choose large RG to prevent loading effect.
RG = 1 M Ω

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Example 3
Determine the resistors to be implemented in the
following circuit for mid-point biasing. The parameters
for the JFET are: IDSS = 15 mA and VGS(off) = -8 V.

12 V

RD
D ID
G +V
- DS
RG S ID
RS

Solution

IDQ = IDSS =7.5 mA

2
V
VGSQ = GS(off) = -8 =-2.35 V
3.4 3.4
VDQ = VDD = 12 =6 V
2 2
RG = 1 M Ω
VGSQ = - VS
VSQ = 2.35 V = IDQRS
RS = VSQ / IDQ = 2.35 /7.5 m = 313 Ω
RD = VDD - VDQ / IDQ = 12 - 6 /7.5 m = 800 Ω

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5. Voltage division biasing

VDD

R1 RD
D ID
G +V
- DS
R2 S ID
RS

VS has to be more positive than VG to maintain the

requirement of a reverse biased G-S.

VS = IDRS

 
VG =  R 2  VDD
 R1 + R 2 

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Example 4

Determine ID and VGS for the following voltage division

biased JFET. Given VDD = 12 V, VD = 7 V, RD = 3.3
kΩ, RS = 1.8 kΩ, R1 = 6.8 MΩ and R2 = 1 MΩ.

VDD

RD
R1
ID
VDS
ID
R2
RS

Solution:

   
ID =  VDD - VD  =  12 -7  =1.52 mA
 RD   3.3 k 

   
VG =  R 2  VDD =  1M 12 =1.54 V

R
 1 + R 2  6.8 M +1M 

VS = IDRS = 1.52 m x 1.8 k = 2.74 V

VGS = VG – VS = 1.54 – 2.74 = -1.2 V

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