Analog Circuit Design

Lesson 3
Amplifier with Active Loads

1
 VDD

In the previous lesson, a load RL

RL was used in an amplifier.

D For IC design, this is not desirable

S
because it is by no means easy to
AC
fabricate a desired resistor.

VGS

2
 VDD

IDS

RL VDD/RL

S
AC

Vout = VDS
VDD
VGS

There is another point. We like RL to be large.

3
Yet a large RL will easily drive the transistor out of saturation.
VDD

IDS
RL A large RL.

S
AC
VDD/RL

V
VDD
VGS

4
It will be desirable to have a load curve,
instead of a load line as shown below:

A particular VGS load curve

IDS

VGS

Vout = VDS

5
To achieve the desirable load curve, we may use an active
load, instead of a passive load, such as a resistor.
I
I I = V/R
R A load line
V V = IR
I = V/R
IDS A particular VGSV.

IDS
G
VDS
VGS A load curve

6
VDS
Consider the following PMOS and its current vs voltage curve.

ISD

S for a certain VSG

G VSD
D

VSD

7
 Vout  VDD  VSD
VDD
IDS

S for a certain VSG

G
D

RL V
out

VDD Vout

Thus a PMOS can be an active load for an NMOS. 8

 VDD
Q2
S
G D I
VGS2

D
Q1
G S
AC

Vout

I
VGS1 VSG2 VGS1

VB Vop VA Vout = VDS1

9
 VDD
Q2 I
S VSG2 VGS1
G D I
VGS2 A
D
Q
G S 1
AC

Vout

VGS1
VB Vop VA Vout = VDS1

It is important that both VGS1 and VGS2 have

to be proper.
10
 Assume that VGS1 is too low.
VDD
Q2 I
S
G D I
VGS2

D
Q
G S 1 VGS1
AC

Vout

VGS1 Vout = VDS1

VB VA

11
 VDD
Q2
S
G D I
VGS2

D
Q
Q2, which is a PMOS transistor,
AC
G S 1
is now an active load for Q1.
Vout

VGS1

12
 The I-V Curves of Q1
VDD
Q2 I
S
G D I
VGS2

D
Q
G S 1 VGS1
AC

Vout

VGS1 Vout = VDS1

13
 So for as Q2 is concerned.
VDD
Q2
S ISD2
G D I
VGS2
For a certain VSG2
D
Q
G S 1
AC

Vout

VGS1 VSD2

14
 But, VSD2=VDD-VDS1.
VDD Therefore, the relationship betwee
S
Q2 n ISD2=IDS1 and VDS1=Vout is as foll
VGS2
G D I ows.
D
Q
G S 1
AC

Vout
IDS1=ISD2
VGS1

Vout=VDS1
VDD

15
 Assume that VGS2 is too low.
I
VDD
Q2
S VGS1
G D I
VGS2

D
Q
G S 1

VGS2
AC

Vout

VGS1

VB V A VOUT = V DS1

16
 VDD
Q2
S
G D I
VGS2

D
Q
G S 1
AC

Vout

VGS1

There is another problem: It is not practical to have different

VGS’ all over an IC.

We should minimize the number of such biasing of voltages.

17
 IDS

for a particular VGS

VDS

We used to think that a proper VGS is the only

way to produce this desirable curve.

Actually, there is another way.

Let us focus on the desired current I DS. 18

 For Q2, instead of thinking about a particular V SG
to produce a desired load curve, let us think about
a method to produce a desired ISD as shown
below. VDD

Q2
S
G D I ISD
VGS2

D
G
Q
S 1
Idesired
AC

Vout

VGS1 VSD

19
 VDD
Q2
S
G D I ISD
VGS2

D
Q
S 1
Idesired
G
AC

Vout

VGS1 VSD

How can we obtain such a desired ISD in Q2?

We use the concept of current mirror.
To explain this concept, we need to talk about the
generation of a constant current source.
20
 For an NMOS, its IDS vs VDS curve is as follows for a part
icular VGS.
IDS

for a
particular VGS
D
G

IDS almost a constant

S

Vout=low VDS

Once the transistor is in the saturation region, IDS is

almost a constant.

How can we guarantee that transistor is saturated? 21

To be in saturation VDS  VGS  Vt
region, .

D
G

22
 By connecting D and G, we have
VDS = VGS .
D
Thus VGS – Vt = VDS – Vt .
G

圖 This ensures that VDS > VGS – Vt .

H
S
The transistor must be in the saturation re
gion now.

23
 VDD Let Id denote the IDS desired.
The transistor is now in
RC Id saturation.
Thus
1 W
I d  k'n ( )(VGS  Vt ) 2      (1)
D 2 L
G S
VDD V DS VDD  VGS
Id      (2)
RL RL

Given Id, find VGS through (1)

Substituting VGS into (2) gives RL.

24
 Current Mirror
Id
VDD Suppose Q1 and Q2 have the same
I2 Vt.

Assume that Q2 is in saturation.

D D

Q1 Q2
Note that VGS1 = VGS2
G G
Then
S S
I2 ( W2
L2 )
 W
Id ( 1 L1 )

If W2 = W1 and L2 = L1, I2 = Id.

By adjusting W2 and L2, we can25

produce desired currents.
 A CMOS Amplifier
VDD VDD
Q2, Q3: PMOS
Q1: NMOS

Q3 Q2
Complementary MOS
(CMOS)

Id Q1
Vout
Vin

26
 Important characteristics:
(1) Q3 is in saturation and therefo
re produces a desired current.
VDD VDD
(2) VSG3 = VSG2. Thus I2 will be Id
I2
if it is in saturation.
Q3 Q2
(3) Whether Q2 is in saturation
or not is determined by Vin.

Id Q1
Vout
Vin

27
 For Q2, we have
ISD2
VDD VDD

ISD2

Id
Q3 Q2

Id Q1
Vout
Vin
VSD2

28
 For Q1: VDS1 = Vout =VDD-VSD2
We first plot ISD2 vs –VSD2
ISD2
VDD VDD

ID
Q3 Q2

Id Q1
Vout -VSD2
Vin

29
 We then plot ISD2 vs Vout
Vout = VDD-VSD2
ISD2
VDD VDD

Id
Q3 Q2

Id Q1
Vout
Vin Vout
VDD

30
 For Q1, IDS1 = ISD2
IDS1 = ISD2
Ｂ

VGS1

VDD VDD

Vout = VDS1
VB Vop VA
(ideal)
Q3 Q2

Id Q1
Vout
Vin
31
 IDS1 = ISD2
Ｂ

VGS1

Vout = VDS1
VB Vop VA
(ideal)

As VGS1 increases, Vout decreases, rather slowly until Vo

ut = VA.

Then Vout drops sharply to VB

An ideal VGS1 makes VOP = ½(VA + VB) 32

 Vout = VDS1

VDD VDD

Q3 Q2

Id Q1 VA VB
Vout Vin = VGS1
Vin

33
 We now try to analyze the
circuit.
The small signal equivalent
VDD VDD
circuit is as follows:

G1 ` `
Q3 Q2

gmvin r01 r02 vout

vin
Id Q1
Vout
Vin

s1

34
 A Typical CMOS Amplifier
For all transistors
VDD VDD
W  0.35
L  10
Q3 Q2

Q4 Q1
Vout
0.7v Vin
0.7v
35
 Example 3-1
The Performance of a CMOS
Amplifier

• We test the performance of a CMOS

amplifier.

• The gain is 30.

36
 .protect
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VDD 1 0 3.3v

VDD=3.3V .param W1=10u W2=10u W3=10u W4=10u

M1 2 3 0 0
1 +nch L=0.35u W='W1' m=1 AD='0.95u*W1'

L=0.35u L=0.35u +PD='2*(0.95u+W1)' AS='0.95u*W1' PS='2*(0.95u+W1)'

M2 2 4 1 1
M3 M2 W =10u
W3=10u 2 +pch L=0.35u
+W='W2' m=1 AD='0.95u*W2' PD='2*(0.95u+W2)'
4 +AS='0.95u*W2' PS='2*(0.95u+W2)'
2 out M3 4 4 1 1
L=0.35u +pch L=0.35u
5 W4=10u 3
+W='W3' m=1 AD='0.95u*W3' PD='2*(0.95u+W3)'
L=0.35u +AS='0.95u*W3' PS='2*(0.95u+W3)'
Vbias=0.7V
VGS4=0.7V M4 M1 M4 4 5 0 0
Vin=0.7V
VGS1=0.7V
W1=10u +nch L=0.35u
6 +W='W4' m=1 AD='0.95u*W4' PD='2*(0.95u+W4)'
Vs
Vin +AS='0.95u*W4' PS='2*(0.95u+W4)'

VGS1 3 6 0.7v
VGS4 5 0 0.7v
Vin 6 0 sin(0v 0.01v 10Meg)

.tran 0.1ns 600ns

.end
37
The gain is 30 which is higher than an NMOS with a resistive load.

38
 Example 3-2
The Operating Point of the
Amplifier
• It is important to find the operating point of the ci
rcuit. To do this, we need to find the load curve
of M2.
• We have to add a dummy resistor Rdm which is
of 0 ohm to the circuit.
• Later, when we perform SPICE simulation, we a
sk the system to display the current going throug
h Rdm.
• This is a standard trick.

39
40
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.op PROBE I(M1) I(Rdm)
.options nomod post

VDD 1 0 3.3v Note this statement.

.param W1=10u W2=10u W3=10u W4=10u
This gives the load curve
M1 2 3 0 0 of M2.
+nch L=0.35u W='W1' m=1 AD='0.95u*W1'
+PD='2*(0.95u+W1)' AS='0.95u*W1' PS='2*(0.95u+W1)'
M2 2 4 1_1 1
+pch L=0.35u
+W='W2' m=1 AD='0.95u*W2' PD='2*(0.95u+W2)'
+AS='0.95u*W2' PS='2*(0.95u+W2)'
M3 4 4 1 1
+pch L=0.35u
+W='W3' m=1 AD='0.95u*W3' PD='2*(0.95u+W3)'
+AS='0.95u*W3' PS='2*(0.95u+W3)'
M4 4 5 0 0
+nch L=0.35u
+W='W4' m=1 AD='0.95u*W4' PD='2*(0.95u+W4)'
+AS='0.95u*W4' PS='2*(0.95u+W4)'

V2 2 0 0v
VGS1 3 6 0.7v
VGS4 5 0 0.7v
Vin 6 0 0v
.DC V2 0 3.3v 0.1v
.PROBE I(M1) I(Rdm)
Rdm 1 1_1 0

.end
41
Red curve is the I-V curve of M1 and blue curve is the load curve of M2.

42
 Example 3-3
I-V Curves of M1 and Load Curve
of M2.

• We draw I-V curves for different

VGS1’s.

43
.protect
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VDD 1 0 3.3v

.param W1=10u W2=10u W3=10u W4=10u

M1 2 3 0 0
+nch L=0.35u W='W1' m=1 AD='0.95u*W1'
+PD='2*(0.95u+W1)' AS='0.95u*W1' PS='2*(0.95u+W1)'
M2 2 4 1_1 1
+pch L=0.35u
+W='W2' m=1 AD='0.95u*W2' PD='2*(0.95u+W2)'
+AS='0.95u*W2' PS='2*(0.95u+W2)'
M3 4 4 1 1
+pch L=0.35u
+W='W3' m=1 AD='0.95u*W3' PD='2*(0.95u+W3)'
+AS='0.95u*W3' PS='2*(0.95u+W3)'
M4 4 5 0 0
+nch L=0.35u
+W='W4' m=1 AD='0.95u*W4' PD='2*(0.95u+W4)'
+AS='0.95u*W4' PS='2*(0.95u+W4)'

V2 2 0 0v
VGS1 3 6 0v
VGS4 5 0 0.7v
Vin 6 0 0v
.DC V2 0 3.3v 0.1v SWEEP VGS1 0.7 0.75v 0.025v
.PROBE I(M1) I(Rdm)
Rdm 1 1_1 0

.end
44
Different I-V curves.

45
 Example 3-4
The Testing of the Stability of the
Amplifier by Shifting the VGS1 and
VGS4 a Little
• We shift the VGS1 and VGS4 a little bit to see
whether this will greatly influence the
performance of the amplifier.

• The result shows the amplifier is quite stable.

The gain is not changed.
46
.protect
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VDD 1 0 3.3v

.param W1=10u W2=10u W3=10u W4=10u

M1 2 3 0 0
+nch L=0.35u W='W1' m=1 AD='0.95u*W1'
+PD='2*(0.95u+W1)' AS='0.95u*W1' PS='2*(0.95u+W1)'
M2 2 4 1 1
+pch L=0.35u
+W='W2' m=1 AD='0.95u*W2' PD='2*(0.95u+W2)'
+AS='0.95u*W2' PS='2*(0.95u+W2)'
M3 4 4 1 1
+pch L=0.35u
+W='W3' m=1 AD='0.95u*W3' PD='2*(0.95u+W3)'
+AS='0.95u*W3' PS='2*(0.95u+W3)'
M4 4 5 0 0
+nch L=0.35u
+W='W4' m=1 AD='0.95u*W4' PD='2*(0.95u+W4)'
+AS='0.95u*W4' PS='2*(0.95u+W4)'

VGS1 3 6 0.725v
VGS4 5 0 0.725v
Vin 6 0 sin(0v 0.01v 10Meg)

.tran 0.1ns 600ns

.end
47
The VGS1 and VGS4 are both shifted to a slighter higher value. The gain is the same.

48
 Example 3-5
More I-V Curves

• More I-V curves are obtained.

49
.protect
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VDD 1 0 3.3v

.param W1=10u W2=10u W3=10u W4=10u

M1 2 3 0 0
+nch L=0.35u W='W1' m=1 AD='0.95u*W1'
+PD='2*(0.95u+W1)' AS='0.95u*W1' PS='2*(0.95u+W1)'
M2 2 4 1_1 1
+pch L=0.35u
+W='W2' m=1 AD='0.95u*W2' PD='2*(0.95u+W2)'
+AS='0.95u*W2' PS='2*(0.95u+W2)'
M3 4 4 1 1
+pch L=0.35u
+W='W3' m=1 AD='0.95u*W3' PD='2*(0.95u+W3)'
+AS='0.95u*W3' PS='2*(0.95u+W3)'
M4 4 5 0 0
+nch L=0.35u
+W='W4' m=1 AD='0.95u*W4' PD='2*(0.95u+W4)'
+AS='0.95u*W4' PS='2*(0.95u+W4)'

V2 2 0 0v
VGS1 3 6 0v
VGS4 5 0 0.7v
Vin 6 0 0v
.DC V2 0 3.3v 0.1v SWEEP VGS1 0.68 0.72v 0.01v
.PROBE I(M1) I(Rdm)
Rdm 1 1_1 0 50
.end
More I-V Curves.

51
 Example 3-6
VDS1 – VGS1
• We like to know how VGS1 influences
VDS1.
• It turns out that there is a narrow region for
us to bias our transistor appropriately and
we have indeed chosen this region. In this
region, the input/output relationship is
quite linear.
• This region is VGS1 between 0.65V to
0.77V.
52
.protect
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VDD 1 0 3.3v

.param W1=10u W2=10u W3=10u W4=10u

M1 2 3 0 0
+nch L=0.35u W='W1' m=1 AD='0.95u*W1'
+PD='2*(0.95u+W1)' AS='0.95u*W1' PS='2*(0.95u+W1)'
M2 2 4 1 1
+pch L=0.35u
+W='W2' m=1 AD='0.95u*W2' PD='2*(0.95u+W2)'
+AS='0.95u*W2' PS='2*(0.95u+W2)'
M3 4 4 1 1
+pch L=0.35u
+W='W3' m=1 AD='0.95u*W3' PD='2*(0.95u+W3)'
+AS='0.95u*W3' PS='2*(0.95u+W3)'
M4 4 5 0 0
+nch L=0.35u
+W='W4' m=1 AD='0.95u*W4' PD='2*(0.95u+W4)'
+AS='0.95u*W4' PS='2*(0.95u+W4)'

VGS1 3 6 0v
VGS4 5 0 0.7v
Vin 6 0 0v
.DC VGS1 0 3v 0.1v
.end

53
VDS1 – VGS1 curve. X-axis is VGS1 and Y-axis is VDS1. Note that VDS1
suddenly drops, a property very useful for amplifiers. Also good for an inverter.
We must put the bias inside the appropriate narrow region.

54
 Example 3-7
An inappropriate operating point

• We lower the VGS1 to 0.65V.

• The performance is very bad at this point.

• The gain is reduced to 4.

55
 .protect
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VSG1=0.65v .op
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Gain=4 VDD 1 0 3.3v

VDD=3.3V .param W1=10u W2=10u W3=10u W4=10u

M1 2 3 0 0
1 +nch L=0.35u W='W1' m=1 AD='0.95u*W1'

L=0.35u L=0.35u +PD='2*(0.95u+W1)' AS='0.95u*W1' PS='2*(0.95u+W1)'

M2 2 4 1 1
M3 M2 W =10u
W3=10u 2 +pch L=0.35u
+W='W2' m=1 AD='0.95u*W2' PD='2*(0.95u+W2)'
4 +AS='0.95u*W2' PS='2*(0.95u+W2)'
2 out M3 4 4 1 1
L=0.35u +pch L=0.35u
5 W4=10u 3
+W='W3' m=1 AD='0.95u*W3' PD='2*(0.95u+W3)'
L=0.35u +AS='0.95u*W3' PS='2*(0.95u+W3)'
Vbias=0.7V
VGS4=0.7V M4 M1 M4 4 5 0 0
Vin=0.7V
VGS1=0.65V
W1=10u +nch L=0.35u
6 +W='W4' m=1 AD='0.95u*W4' PD='2*(0.95u+W4)'
Vs
Vin +AS='0.95u*W4' PS='2*(0.95u+W4)'

VGS1 3 6 0.65v
VGS4 5 0 0.7v
Vin 6 0 sin(0v 0.01v 10Meg)

.tran 0.1ns 600ns

.end
56
VGS1 is 0.65V. The gain becomes as low as 4.

57
 Example 3-8
Yet Another Operating Point

• The VGS1 is now set to 0.75V.

• The gain is 27 which is all right.

58
 .protect
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VSG1=0.75v .options nomod post

Gain=27 VDD 1 0 3.3v

VDD=3.3V .param W1=10u W2=10u W3=10u W4=10u

M1 2 3 0 0
1 +nch L=0.35u W='W1' m=1 AD='0.95u*W1'

L=0.35u L=0.35u +PD='2*(0.95u+W1)' AS='0.95u*W1' PS='2*(0.95u+W1)'

M2 2 4 1 1
M3 M2 W =10u
W3=10u 2 +pch L=0.35u
+W='W2' m=1 AD='0.95u*W2' PD='2*(0.95u+W2)'
4 +AS='0.95u*W2' PS='2*(0.95u+W2)'
2 out M3 4 4 1 1
L=0.35u +pch L=0.35u
5 W4=10u 3
+W='W3' m=1 AD='0.95u*W3' PD='2*(0.95u+W3)'
L=0.35u +AS='0.95u*W3' PS='2*(0.95u+W3)'
Vbias=0.7V
VGS4=0.7V M4 M1 M4 4 5 0 0
Vin=0.7V
VGS1=0.75V
W1=10u +nch L=0.35u
6 +W='W4' m=1 AD='0.95u*W4' PD='2*(0.95u+W4)'
Vs
Vin +AS='0.95u*W4' PS='2*(0.95u+W4)'

VGS1 3 6 0.75v
VGS4 5 0 0.7v
Vin 6 0 sin(0v 0.01v 10Meg)

.tran 0.1ns 600ns

.end
59
VGS1=0.75V. The gain is 27 which is quite good.

60
 Example 3-9
Load Curves of M4, the Current
Source

• Transistor M4 is a current source. We

investigate its I-V curve and its load curve.
• The current is found to be 100u.
• Note that the current in M2 is also roughly
100u which shows that M2 functions as a
current mirror.
61
.protect
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VDD 1 0 3.3v

.param W1=10u W2=10u W3=10u W4=10u

M1 2 3 0 0
+nch L=0.35u W='W1' m=1 AD='0.95u*W1'
+PD='2*(0.95u+W1)' AS='0.95u*W1' PS='2*(0.95u+W1)'
M2 2 4 1_1 1
+pch L=0.35u
+W='W2' m=1 AD='0.95u*W2' PD='2*(0.95u+W2)'
+AS='0.95u*W2' PS='2*(0.95u+W2)'
M3 4 4 3_1 1
+pch L=0.35u
+W='W3' m=1 AD='0.95u*W3' PD='2*(0.95u+W3)'
+AS='0.95u*W3' PS='2*(0.95u+W3)'
M4 4 5 0 0
+nch L=0.35u
+W='W4' m=1 AD='0.95u*W4' PD='2*(0.95u+W4)'
+AS='0.95u*W4' PS='2*(0.95u+W4)'

V4 4 0 0v
VGS1 3 6 0.7v
VGS4 5 0 0.7v
Vin 6 0 0v
.DC V4 0 3.3v 0.1v
.PROBE I(M4) I(Rm3)
Rdm 1 1_1 0
Rm3 1 3_1 0
62
.end
Red curve is the load curve of M3 and blue curve is the I-V curve for M4.
Note that M3 is like a diode because VGD3=0.

63
 Example 3-10
The Changing of VGS4

• Since M4 functions as a current source,

we change VGS4 from 0.7V to 0.75V to
produce another current source.

• This produces a disastrous result.

• The gain is only 6 now.

64
65
.protect
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VDD 1 0 3.3v

.param W1=10u W2=10u W3=10u W4=10u

M1 2 3 0 0
+nch L=0.35u W='W1' m=1 AD='0.95u*W1'
+PD='2*(0.95u+W1)' AS='0.95u*W1' PS='2*(0.95u+W1)'
M2 2 4 1 1
+pch L=0.35u
+W='W2' m=1 AD='0.95u*W2' PD='2*(0.95u+W2)'
+AS='0.95u*W2' PS='2*(0.95u+W2)'
M3 4 4 1 1
+pch L=0.35u
+W='W3' m=1 AD='0.95u*W3' PD='2*(0.95u+W3)'
+AS='0.95u*W3' PS='2*(0.95u+W3)'
M4 4 5 0 0
+nch L=0.35u
+W='W4' m=1 AD='0.95u*W4' PD='2*(0.95u+W4)'
+AS='0.95u*W4' PS='2*(0.95u+W4)'

VGS1 3 6 0.7v
VGS4 5 0 0.75v
Vin 6 0 sin(0v 0.01v 10Meg)

.tran 0.1ns 600ns

.end

66
VGS4 is now set to be 0.75V. This will produce another current source.
The gain is reduced to 6.

67