Chapter 1c

“FIELD EFFECT TRANSISTOR”

FET small signal model, FET amplifier analysis.

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 JFET small-signal model at low frequency
Id
Id G D
JFET
D 
G Vgs Vds Small signal
gmVgs rd
S model at LF
S
Definitions of important parameters in the model (ac quantities) :

g m  Forward transconductance
I D I D
  , at constant VDS
VGS VGS rd  Drain resistance
VDS VDS
  Amplificat ion factor   , at constant VGS
I D I D
 VDS V
   DS  g m rd , at constant ID
VGS VGS

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Transconductance, gm
ID

The relationship of
IDSS VGS(input) to ID(output) is
- gm is given by the slope of called transconductance
the transfer characteristic

Q ID ~ Id

VGS
VGS(OFF)
VGS ~ Vgs

For Enhancement-type MOSFETs, ID = K(VGS – VGST)2,

then gm = 2K(VGS – VGST)
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 Mathematical Definition of gm
I D I D  2 I DSS  VGS  Recall Shockley’s equation,
gm     1
  
VGS VGS  VGS (OFF )  VGS (OFF )  ID = IDSS (1-VGS/VGS(OFF))2

2I  VGS 
(i) When VGS =0V, g m0   DSS  g m  g m0 1 
VGS (OFF ) 
Recall Shockley’s equation,
 VGS(OFF) 
ID = IDSS (1-VGS/VGS(OFF))2
(ii) When  V  I
g m  g m0 1    g m0
VGS ID GS D
1  ,
VGS(OFF) I DSS  V  I DSS
 GS(OFF) 

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Drain resistance, rd
ID
5

ID ~ Id

VDS ~ Vds

VDS

rd  Drain resistance
V V
 DS  DS , at constant VGS The more horizontal the
ID ID
curve, the greater is rd value.
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FET Small Signal Analysis
 Approximate the behavior of nonlinear devices with
linear equations

 Start with the small signal model.

 Short all DC supply to ground.
 Short all capacitor with sufficiently large capacitance.
 Insert the biasing resistors, load and source resistance.
 Re-draw the circuit to ease analysis.
 Use KCL & KVL to determine the parameters.
 Interested parameter: Input and output impedances,
voltage & current gains.

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Model 1: JFET Common-Source Fixed-bias Configuration

IRD
Io

ID
Ii
There is a 180 phase shift
between input and output

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 Derivations:
Id Io
Ii
IRD,ac

(i) Input impedance:

Zi  RG (iii) Voltage gain, AV= VO/Vi :

(ii) Output impedance: VO  ( g mVgs ) Z O

Zo  rd || R D
VO  A v  g m ZO  -gm (rd || R D )
ZO  Vi 0V or
IO or

Zo  R D A v  g m R D
rd  10R D rd  R D

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Example 1
For IDSS = 10mA, Vp=VGS(OFF) = -8V and  = 46.875, rd=25kOhm, VGSQ=-2V
Find:
i) gm
ii) Zi + 20V
iii) Zo
v) AV 2k
IRD
vi) AV (ignoring rd)
Io
ID Vo
D
Ii G
Vi
S
1M

2V

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Model 2: Common-Source Self-Bias Configuration with
Rs Bypassed

IRD

Io
ID
Ii
There is a 180 phase shift between
input and output

Id Io
Ii

IRD,ac

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 Derivations (Similar to model 1):
Id Io
Ii 11

IRD,ac

Vi  Vgs  0 V

(i) Input impedance: (iii) Voltage gain, AV= VO/Vi :

Zi  RG
VO  ( g mVgs )Z O
(ii) Output impedance:
Zo  rd || R D  A v  g m ZO  -gm (rd || R D )
VO
ZO  Vi 0V or or
IO
Zo  R D A v  g m R D
rd  R D
rd  R D
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Model 3: Common-Source Self-Bias Configuration
with Rs UnBypassed (no by pass Cs)
IRD

Ii ID
- Removing Cs affects Io
the gain of the circuit.

Id
Ii

IRD,AC
Ir

IO + IRD,AC

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Derivations:
(i) Input impedance:
Ii G D Id Io
Zi  RG Ir
IRD,ac
RG gmVgs rd
Vi RD Vo
(ii) Output impedance:
S
V I RD ,ac RD IS
ZO  O Vi  0V  (1) RS
IO
IO IO
Zi IO + IRD,ac Zo
Find expression of IO in terms of IRD,ac

I O  I r  g mVgs  I RD ,ac (2)  (2) becomes :

VO  Vgs
where, IO   g mVgs  I RD ,ac (3)
I r  Vrd / rd rd
Vrd  VO  VRS as VO   I RD ,ac RD
 VO  (Vgs ) and Vgs  ( I O  I RD ,ac ) RS Vi  0
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 RD RS
 (1  g m RS   )
Substituting VO and Vgs rd rd
into (3), we will get: IO  I RD ,ac (4)
R
1  g m RS  S
rd
(4) Into (1):
[1  g m RS  RS / rd ]
Zo  RD or Z o  RD rd 10 RD
[1  g m RS  RS / rd  RD / rd ]

(iii) Voltage gain, Av= Vo/Vi:

VO   I RD ,ac RD (1)
Solve for (2) & rearrange, will get:
with I RD ,ac  I r  g mVgs (2)
g mVi
VO  VRS I RD ,ac  (3)
where , Ir  RD  RS
rd 1  g m RS 
rd
Vgs  Vi  VRS
14 VRS  I RD ,ac Rs
 g mVi
Substituting (3) into (1), we will get: VO  ( ) RD
RD  RS
1  g m RS 
rd
VO g m RD
 Av  
Vi RD  RS
1  g m RS 
rd

g m RD
or Av   rd  ( R  R )
1  g m RS D S

 The negative sign indicates that phase shift of 180o

between input and output voltage.
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Model 4: Common source Voltage Divider Configuration

RD IRD
IRD Io
R1
ID Vo
ID Io D
Ii G
Ii Vi
S
R2

Ii Id Io

IRD,ac

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 Derivations:
Ii Id Io
IRD,ac

(i) Input impedance: (iii) Voltage gain, AV= VO/Vi :

Z i  R 1 || R 2 VO  ( g mVgs ) Z O

(ii) Output impedance:  A v  g m ZO  -gm (rd || R D )

Z o  rd || R D or

Zo  R D A v  g m R D
rd  R D
rd  10R D

17 a phase shift of 180o exists between Vi & Vo

 Model 5: JFET Source Follower (Common drain) Configuration
VDD
ID ID
D D
Ii G Ii G
Vi Vi
S S
IS Vo IS
RG RG Vo
Io Io
RS IRS RS IRS

Zi
Zo

Ii G D Ii G S Is Io
Vi
VGS Irs
gmVgs Vi RG
rd gmVgs rd RS Vo
RG S
Vo D
VGS Id
RS Zi Z’o Zo

Zi

18 Zo
 Derivations:
Ii G S Is Io

Irs  Z O  Z'O // rd // RS
Vi RG
I= gmVgs rd RS Vo

D (iii) Voltage gain, AV= VO/Vi :

Id
Zi Zo
Z’o where ,

(i) Input impedance, Zi = RG Vgs= Vi-Vo

Vo = gmVgs (rd//Rs) when Io = 0 (no load)
(ii) Output impedance, Zo
= gm (Vi – Vo)(rd//RS)
Vo
Zo  G is grounded Rearrange → Vo (1 +gm(rd//RS)) = Vigm(rd//RS)
Io Vi  0
Vo g (r // RS )
• Thus, voltage across I is – Vgs  Av   m d
Vi 1  g m (rd // RS )
Vgs 1
so Z o ' | | Input and output voltages are in phase. The voltage gain
g mVgs g m is close to unity but always less than unity.
 Model 6: JFET Common Gate Configuration
Ii IS ID Io

IRS

Vo
Z’O IRD

The input is on
the source and
the output is on
the drain. Is Id Io
Ii
Irs

Z’i IRD,ac

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 Derivations:
Ii Is Id Io

Irs

Z’i IRD,ac

(i) Input Impedance, Zi:

• Determine Z’i first
where, Z’i = V’/I’
V ' I ' RD
I '  I rd  g mVgs   g mVgs
rd
Since Vgs= -V’

V ' I ' RD
I'  g m (V ' )
rd
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Rearranging, (ii) Output impedance:

RD Vo
[1  ] Zo  G is grounded
V' rd Io
Z 'i   Vi  0
I ' [g  1 ]
m
rd And thus, Z o  rd || R D

And thus,
Z'o  rd or, Zo  R D
rd  R D
Z i  Rs // Z 'i
R Ii gmVgs= 0
Id Io
[1  D ] Is S D

rd Irs -
 Rs // RD
1
[gm  ] Vi=0 RS rd
rd Vgs= 0
+ G
IRD,ac

or,
Z’o Zo

Z i  RS //(1 / g m ) rd  RD

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 (iii) Voltage gain, AV= VO/Vi :

VO   I RD ,ac RD  ( g mVgs  I rd )RD (2a )

and
VO  Vi
I rd  (2b) & Vgs  Vi (2c)
rd
Substitute (2b) & (2c) into (2a), solving:
RD R
VO [1  ]  Vi [ g m RD  D ]
rd rd
RD
[ g m RD  ]
VO rd Av  g m RD rd 10 RD
 Av   or
Vi RD
[1  ]
rd

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