Field Effect Transistor (FET)

So, far we have gone through BJT construction, operation, biasing, and amplifications

➢ BJT has three terminals (Base, collector, & Emitter)

➢ Bipolar  two carriers (electrons & holes), and hence called bipolar

Now we would like to discuss the field effect transistors

In field effect transistor only one type of carrier contributes the current Unipolar Transistor
• Junction Field Effect Transistor (JFET)

• Metal Oxide Field Effect Transistor (MOSFET)

FET/MOSFET also has three terminals (Gate, Drain, & Source)

The Gate  Base, Drain  Collector, & Source  Emitter

Difference between the BJT and FET

The BJT is a current control device whereas the FET is a voltage control device.
The input current through any one of the three terminals of the BJT actually determines the current flow
through the other two terminals i.e. emitter current must be equal to the base and collector.
On the contrary, there is no actual flow of gate current in the FET. In the BJT the collector current is the
direct function of the input(base) current i.e. 𝐼𝐶 ∝ 𝐼𝐵 , where as the drain current in the FET is direct
function of the gate to source voltage (input control voltage) i.e. 𝐼𝐷 ∝ 𝑉𝐺𝑆 as indicated in Fig. 4.1.

Collector (C) Drain (D)

IC + +
ID

IB Gate (G) FET

Base (B) BJT VCC VDS
+ +
VBE IE VGS IS
− − − −
Emitter (E) Source (S)

Fig. 1 BJT and FET

Advantages of FETs
1. Both types of carriers (electrons and holes) contribute to current flow in BJT, whereas in FET
only one type of carrier, either n (n-channel) or p (p-channel), contributes to current flow. For
this reason, FET is called unipolar device. Vacuums tube is another example of unipolar
device.
2. It is simple to fabricate FET in IC form and is efficient in working.
3. The FET is smaller in size and hence high-density devices are fabricated using FETs w.r.t. BJT.
4. The noise due to temperature effect is not present in FET.
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 5. An insulator (SiO2) isolates the channel from the gate of the MOSFET; the input resistance of the
FET is very high (of the order of 100M) whereas input resistance of BJT is of the order of few
ohms to hundreds of ohms.
6. The FET has negative temperature coefficient of resistance and hence has better stability against
temperature.
7. The FET does not exhibit offset voltage at zero drain current and hence works as an excellent
signal chopper.

Disadvantages of JFET
1. As the FET has high input resistance, the gate voltage has less control over its drain current and
hence the voltage gain of FET amplifier is low w.r.t. the BJT amplifier.
2. The gain bandwidth product of the FET amplifier is low w.r.t. the BJT amplifier.

BASIC CONSTRUCTION

Depletion VGS
G G
+
𝑛 𝑛+
S p-type D S p-type D

𝑛+ 𝑛+
G G

𝑝+ 𝑛 D
D
S D G
G
R R R R R R R S
S
n-channel p-channel
𝑝+

Working Principle of JFET

𝑉𝐺𝑆 = 0, and 𝑉𝐷𝑆 very small (fraction of volts), depletion width very narrow from both sides and the
maximum drain current flows 𝐼𝐷𝑆 = 𝐼𝐷 through the channel. 𝐼𝐷𝑆 = 𝐼𝐷 depends both 𝑉𝐺𝑆 = 0, 𝑉𝐷𝑆 , and
the channel resistance, say 𝑟𝑑 .
Increasing 𝑉𝐺𝑆 , channel width decreases, 𝑉𝐷𝑆 very small (fraction of volts), depletion symmetrical
from both sides.
The 𝐼𝐷 versus 𝑉𝐷𝑆 characteristics shown in Fig. 4.3 (d) remains a straight line for low voltage across the
JFET.

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This condition is called the physical pinch-off and is illustrated in Fig. 4.3 (c). The pinch-off voltage is
defined as;
𝑉𝑃 = 𝑉𝐺𝑆(𝑂𝐹𝐹) | (4.1)
𝐼𝐷 =0,𝑉𝐷𝑆 =𝑣𝑒𝑟𝑦 𝑠𝑚𝑎𝑙𝑙

D D
𝑛 𝑛 ID=0
ID1 𝑛 ID2

VDD VDD
G 𝑝 +
𝑝 + VDD G 𝑝+ 𝑝+
small G 𝑝+ 𝑝+ 𝑠𝑚𝑎
small

VGS
VGS
S S
𝑆
(a) (b) (c)
ID
VVR range
Linear Range VGS = 0V
Drain current

or 𝑂ℎ𝑚𝑖𝑐 𝑟𝑎𝑛𝑔𝑒
VGS= -1V
VGS= -2V
VGS= -3V
VGS= -4V VP
DS V
(d)
Fig. 4.3 Channel width variation and physical pinch-off with small 𝑉𝐷𝑆

4.5 Operation of JFET beyond linear range

Now, 𝑉𝐺𝑆 = 𝐾 (i.e. less negative) than 𝑉𝑃 and 𝑉𝐷𝑆 is increased. The semiconductor channel exhibits a
resistance. The amount of voltage applied (𝑉𝐷𝐷 ) across the channel is distributed uniformly from source
to the drain having zero voltage at the source and 𝑉𝐷𝐷 at the drain as indicated in Fig. 4.4.

𝑉𝐺𝑆
𝑉𝐷𝑆 + 𝑉𝐺𝑆 𝑉𝐷𝐷

𝑉𝐷𝑆

𝑥
0 L
Fig. 4.4 JFET with 𝑉𝐺𝑆 ≥ 𝑉𝑃 .

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When the reverse bias at drain end 𝑉𝐷𝐺 falls below the pinch-off voltage (𝑉𝑃 ), the channel is pinched off
at the drain end and the drain current saturates.
Here, the pinch-off is misnomer. The word pinch-off stands for zero drain current, but here it is
maximum value of constant current. The reverse bias at the drain end will be 𝑉𝐷𝑆 = 𝑉𝐷𝐷 and at the
source end the reverse bias = 0V. Hence, the formation of depletion region is tapered shape as shown in
Figs.4.4 by dotted line.
After pinch-off increasing VDS does not alter the shape of the channel and ID remains constant for 𝑉𝐷𝑆 =
𝑉𝑃 .
This is the value of saturated drain-source current (𝐼𝐷𝑆𝑆 ) is specified in the data sheet of the JFET. It is
defined as;
𝐼𝐷𝑆𝑆 = 𝐼𝐷 |𝑉𝐺𝑆 =0, 𝑉𝐷𝑆 >𝑉𝑃 (4.2)

𝐷
   
      𝐼 =𝐼
𝐷 𝐷𝑆𝑆
 
   𝑉𝐷𝐷
𝑉𝐺𝑆 = 0
  = 𝑉𝑃
𝐺
 +
𝑝+  𝑝
 
 
𝑆

𝑛 𝑉𝐺𝑆 (𝑠𝑚𝑎𝑙𝑙) and large 𝑉𝐷𝑆

Fig. 4.5 Channel shape with

The drain to source voltage at pinch-off can be expressed as;

𝑉𝐷𝑆 = 𝑉𝐺𝑆 − 𝑉𝑃𝑂 (4.3)
𝑉𝐷𝑆 = 0, 𝑓𝑜𝑟 𝑉𝑃𝑂 = 𝑉𝐺𝑆(𝑂𝐹𝐹) , and 𝑉𝐷𝑆 = −𝑉𝑃𝑂 𝑓𝑜𝑟 𝑉𝐺𝑆 = 0. (4.4)
The gate voltage at which the channel is cut-off is called gate-source cut-off voltage 𝑉𝐺𝑆(𝑂𝐹𝐹) and
drain current becomes zero.
ID
VDS  (VGS-VP0) VDS  (VGS-VP0)
Avalanche breakdown

Linear range Saturation range

Saturation level
IDSS 𝑃𝑖𝑛𝑐ℎ 𝑜𝑓𝑓 𝑟𝑒𝑔𝑖𝑜𝑛 𝑃𝑖𝑛𝑐ℎ 𝑜𝑓𝑓 𝑟𝑒𝑔𝑖𝑜𝑛
Ohmic VGS=0
𝑃𝑖𝑛𝑐ℎ 𝑜𝑓𝑓 𝑟𝑒𝑔𝑖𝑜𝑛
range Current saturation due to
rd pinch-off at drain end
n-channel
resistance Increasing resistance due to
narrowing of channel
VDS
VP0
Fig. 4.6 Plot of 𝐼𝐷 -𝑉𝐷𝑆 for VGS = 0

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 Figure 4.7 shows a set of output characteristics for different values of 𝑉𝐺𝑆 . The transfer curve is
drawn as in Fig. 4.8. The voltage 𝑉𝐷𝑆 at which saturation occurs for 𝑉𝐺𝑆 = 0 is called the pinch-off
voltage 𝑉𝑃𝑂 . It is about –4V in Figs.4.7 and 4.8. For various values of 𝑉𝐺𝑆 , the locus of 𝑉𝑃𝑂 is drawn as
the dotted exponential curves in Fig. 4.7.

ID Locus of VP
VGS=0=VP+4V
IDSS 
VGS= -0.5V=VP+3.5V


 VGS= -1V=VP+3V

VGS= -2V=VP+2V

VGS  -4V(VP0=0)
VGS= -3V=VP+1V
 VDS
VP0 8 12

Fig. 4.7 Output characteristics of JFET

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