TUTORIAL 8 - JFET

Q1. Explain on the basic operation of the n-channel JFET. Draw the drain
characteristics of the mentioned JFET type and denote the important parameters
on the graph.

Q2. Explain why the JFET is called a unipolar device. Your explanation must be based
on the n-channel or p-channel device which is biased to operate as an amplifier.

Q3. What is one advantage of FET over BJT?

Q4. What is the main advantage of using self-biasing in a JFET amplifier circuit?
Draw the self-biasing circuit.

Q5. How is the drain current controlled in the n-channel JFET? Use illustrations to
help you in giving your explanations.

Q6. For the circuit shown below:

(a) explain in detail on the reason why ID in the saturation region decreases with the
increment of VGG at a fixed VDD.
(b) what will happen if V GG = VGS(off) ?

RD

ID
+ VDS
- VDD
-
-
VGG
Q7. The JFET in the following diagram has the following characteristics, I DSS =
5mA and VGS(off) = -3V . Determine VGSQ and VO if
(a) V G = 0 V
(b) V G = 10 V

+15V

RD
3 kΩ

+
RS +
VG
8 kΩ VO
- 8V -

Q8. Given the drain to ground voltage is equivalent to 5 V for the circuit below.
Calculate I D ,VGS ,VDS and VS for this circuit.

+VDD
9V

R1 RD
10 MΩ 4.7 kΩ
+

VD = 5 V
R2 RS
2.2 MΩ 3.3 kΩ

-
Q9. The JFET in the following diagram has Vp = -3 V and IDSS = 9 mA . Calculate the
value of all the resistors so that VG = 5 V,ID = 4 mA and VD =11V . The design has
0.05 mA flowing through the voltage divider.

+15V

RG1 RD

+
11V
RG2 RS
5V

- -

Q10. The gate current can be ignored for the JFET in the circuit below. If VDD = -20 V,
IDSS =10 mA, IDQ = 8 mA, VGS(off) = 4 V, RS = 0 Ω and RD =1.5 kΩ. Determine:

(i) VGG and

(ii) VDSQ

VDD

RD C2

C1 +
+
RG vo
vi
VGG RS
- -
Q11. For the circuit shown below, RG >> RS1, RS2 ,IDSS = 10 mA, VGS(off) = -4 V, VDD =15 V, VDSQ =10
V and VGSQ = -2 V.
Determine:
(a) VS
(b) RS1
(c) RS2

VDD

ii CC
CC
+ +
iL
RG RS1 +
v in RL vL

RS2 VS -
CS
-
-

Q12. (a)Self-biasing is implemented on the following JFET circuit. Assume that the
gate current can be neglected (IG = 0). Show that if VDD > 0, VGS < 0. This
condition will enable correct device biasing.

(b)If R D = 3 kΩ , R S = 1 kΩ, VDD =15 V and VDSQ = 7 V , calculate IDQ and VGSQ.

VDD

RD
+

VDSQ
-
RG
RS
Q13. The JFET in the following circuit has Vp = -3 V. If VS = -1 V when the device is
in its pinched-off region, calculate IDSS.

VSS

1mA
VS = -1V

-
VDD

Q14. For a JFET that is operating at VGS = -1 V, has Vp = 2 V and IDSS = 8 mA,
determine the variation required in the VGS to increase the ID by 0.4 mA. What is
the variation required in the VGS to reduce the ID by 0.4 mA from the same initial
value. Why is the variation in the VGS different for both cases? What is the JFET
type? Give explanations for your answers.

Q15. (a)Determine the voltages at the terminal of the JFET. Given: VGS(off) = -4 V and
IDSS = 4 mA.

(b)Determine the transistor’s mode of operation, i.e. whether it is in depletion or

enhancement mode. Based on the results from the calculation in (a), give two
reasons for your answer.
11V

R1 RD
100 MΩ 1kΩ
v out
v in

R2
10 MΩ