Supertex inc.

HV7355DB1

150V, 1.5A, Unipolar

Ultrasound Pulser Demoboard

General Description This demoboard datasheet describes how to use the

The HV7355 is a monolithic eight-channel, high-speed,
high voltage, unipolar ultrasound transmitter pulser.
This integrated, high performance circuit is in a single,
8x8x0.9mm, 56-lead QFN package.
The HV7355 can deliver guaranteed ±1.5A source and sink
current to a capacitive transducer with 0 to +150V peak
voltage. It is designed for medical ultrasound imaging and
ultrasound material NDT applications. It can also be used
as a high voltage driver for other piezoelectric or capacitive
MEMS transducers, or for ATE systems and pulse signal
generators as a signal source.
The HV7355’s circuitry consists of controller logic circuits,
level translators, gate driving buffers and a high current and
high voltage MOSFET output stage. The output stages of
each channel are designed to provide peak output currents
typically over ±1.5A for pulsing, with up to 150V swings. The
upper limit frequency of the pulser waveform is dependent
upon the load capacitance. With different capacitance load
conditions the maximum output frequency is about 20MHz.
HV7355DB1 to generate the basic high voltage pulse
waveform as an ultrasound transmitting pulser.
The HV7355 circuit uses DC-coupling from a 3.3V logic input
to output TX0~7 internally, therefore the chip needs three
sets of voltage supply rails: VLL (+3.3V), VDD/VSS (+/-5.0V)
and VPP (up to +150V). The VPP high voltage supply can be
changed rather quickly, compared to the capacitor gate-
coupled driving pulsers. This direct coupling topology of the
gate drivers not only saves two high voltage capacitors per
channel, but also makes the PCB layout easier.
The control signal logic-high voltage should be the same
as the VLL voltage of the IC, and the logic-low should be
referenced to GND.
The HV7355DB1 output waveforms can be displayed using
an oscilloscope by connecting the scope probe to the test
points TX0~7 and GND. The soldering jumper can select
whether or not to connect the on-board dummy load, a
330pF capacitor paralleling with a 2.5kΩ resistor. The test
points can be used to connect the user’s transducer to easily
evaluate the pulser.

Block Diagram
+3.3V +5.0V +5.0 to 150V

+3.3V

VLL AVDD VDD CPF VPP

LR VPF
EN
PWR VSS
EXCLK VDD
MC VPP
CWD
LT
OSC CLKIN
IN0
VPF TX0
40MHz VDD
EN
Waveform Q0 VDD
R2
Generator LT Dummy
Load
CPLD C4
RGND R3
330pF 2.5k
VDD
6 VPP VPP
JTAG GND
LT
IN7
VPF TX7
VDD TX7
CW Q7 VDD
SET Q[7:0]
WAVE LR LT
Data
RTZ LE Latch RGND
FREQ
SEL PWR CS
Shift RGND
EN EN SCK SUB
Register
CW/RTZ Q7 D0
SDO SDI VSUB GND VSS

-5.0V

Doc.# DSDB-HV7355DB1
B070314
Supertex inc.
www.supertex.com

The PCB Layout Techniques
The large thermal pad at the bottom of the HV7355 package
is internally connected to the IC’s substrate (VSUB). This
thermal pad should be connected to 0V or GND externally
on the PCB. The designer needs to pay attention to the con-
necting traces on the outputs TX0~7, as the high-voltage
and high-speed traces. In particular, controlled-impedance
to the ground plane and more trace spacing needs to be ap-
plied in this situation.
High-speed PCB trace design practices that are compatible
with about 50 to 100MHz operating speeds are used for the
demo board PCB layout. The internal circuitry of the HV7355
can operate at quite a high frequency, with the primary speed
limitation being load capacitance. Because of this high
speed and the high transient currents that result when driv-
ing capacitive loads, the supply voltage bypass capacitors
and the driver to the FET’s gate-coupling capacitors should
be as close to the pins as possible. The GND pin should
have low inductance feed-through via connections that are
connected directly to a solid ground plane. The VDD, VSS,
VPP and CPP voltage-supply and/or bypass capacitor pins
can draw fast transient currents of up to 2.0A, so they should
be provided with a low-impedance bypass capacitor at the
chip's pins. A ceramic capacitor of 1.0 to 2.0µF may be used.
Only VPP to GND capacitors need be high voltage. CPF to
VPP capacitors only need be low voltage. Minimize the trace
length to the ground plane, and insert a ferrite bead in the
power supply lead to the capacitor to prevent resonance in
the power supply lines. For applications that are sensitive
to jitter and noise when using multiple HV7355 ICs, insert
another ferrite bead between each chips supply line.
Pay particular attention to minimizing trace lengths and
using sufficient trace width to reduce inductance. Surface
mount components are highly recommended. Since the out-
put impedance of the HV7355’s high voltage power stages
is very low, to obtain better waveform integrity at the load
terminals after long cables, in some cases it may be desir-
able to add a small value resistor in series with the outputs
TX0~7. This will, of course, reduce the output voltage slew
rate at the terminals of a capacitive load. Be aware of the
parasitic coupling from the outputs to the input signal termi-
nals of the HV7355.
Doc.# DSDB-HV7355DB1
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HV7355DB1
This feedback may cause oscillations or spurious waveform
shapes on the edges of signal transitions. Since the input
operates with signals down to 3.3V, even small coupling
voltages may cause problems. Use of a solid ground plane
and good power and signal layout practices will prevent this
problem. Also ensure that the circulating ground return cur-
rent from a capacitive load cannot react with common induc-
tance to create noise voltages in the input logic circuitry.
Testing the Integrated Pulser
The HV7355 pulser demoboard should be powered up with
a DC power supplie that has current limiting functions.
To meet the typical loading conditions, the on-board dummy
load 330pF//2.5kΩ should be connected to the high voltage
pulser output through the solder jumper when using an oscil-
loscope’s high impedance probe. To evaluate different load-
ing conditions, the values of the RC within the current and
power limit of the device may be changed.
In order to drive the user’s piezo transducers with a cable,
one should match the output load impendence properly to
avoid cable and transducer reflections. A 70 to 75Ω coaxial
cable is recommended. The coaxial cable end should be sol-
dered to TX0~7 and GND directly with very short leads. If a
user’s load is being used, the on-board dummy load should
be disconnected by cutting the small shorting copper trace in
between the zeroΩ resistor’s (R2, R12 etc.) pads. They are
shorted by factory default.
All of the on-board test points are designed to work with the
high impedance probe of the oscilloscope. Some probes
may have limited input voltage. When using the probe on
these high voltage test-points, make sure that VPP voltages
do not exceed the probe limit. Using the high impendence
oscilloscope probe for the on-board test points, it is impor-
tant to have short ground leads to the circuit board ground
plane.
Supertex inc.
 B070314
TP1
R2
D3 D4 D5 D6 D7 0 R3

Doc.# DSDB-HV7355DB1
RED YLW YLW GRN RED C4 2.55k
330pF 1W
250V
TP4

TP11
R4 R5 R6 R7 R8 VDD TP8 TP35 TP5 VPP R12
1.0k 1.0k 1.0k 1.0k 1.0k
C14 C12 C13 C5 C8 C9 C27 C6 C28 0 R13
R47 50 TP6 EN 1µ 1µ 1µ 1µF 1µF
1µF 1µF 1µF 1µF C20 2.55k
VCC 160V 160V 160V 160V
R48 50 TP9 330pF 1W
LE 250V
R49 50 TP10 TP14
MC VCC TP2
TP12
HV7355DB1 Schematic

VCC R50 50
SET TP23
R51 50 TP40
CS R18
C19
C18 TP3 0.22 0
VCC R19

16
55
23
48
53
18
49
21
20
52
51
50
19
22
0.22 2.55k
C21
C1 C2 C3 330pF 1W
EX=0

VLL
CPF
CPF
VPP
VPP
VPP
VPP
VPP
VPP
VPP
VPP

VDD
VDD
40MHz X1 022 022 022 250V TP31

AVDD
2 1 4 56 42 VZ2
EN VCC EN TX0
1
TP13 43 TP32

32
31
30
29
28
35
26
15
TX0
J1 VZ3 R23
2 3 41

LE
CS
EN
GND OUT TX1

MC
38 R17 50 TP16

SET
1

VCC
VCC
VCC
IN0 IN0 40 0
37 R21 50 TP20 TX1 R24
R14 2 C29 2.55k
3 IN1 IN1 39 VZ4
1.0k 22 R22 50 TP19 TX2 330pF 1W
J2 1 43 3
CLK IN2 IN2 38 250V
EXCLK 21 R23 50 TP22 TX2
2 4 TP34
W4 IN3 IN3 37 VZ5
R15 TP25 TX3
19 R36 50 5

3
50 IN4 IN4 36
ZE;794ZNaXS66 TP27 JX9577 TX3 TP7
40 18 R39 50 6
SCK IN5 IN5 35 VZ6 R10
39 14 R45 50 TP28 7 TX4
SDO IN6 IN6 34 0 R11
13 R46 50 TP29 8 TX4 2.55k
R20 R20 IN7 IN7 VZ7 C7
33 330pF 1W
50 50 TX5
15 250V
MC MC 32 TP21

GND
GND
GND
WAV
FRE
SEL
ENA
MOD
TDO
TCK
TP18 11 TX5
TP30 LE LE

4
2
3
5
6
7
9 TDI
VCC 31 VZ8 TP26

17
25
10 TMS
24
11
14 TX6
SET SET
9 30 R37
C22 CS CS TX6
12
0.22 SCK SCK 29 VZ9 0 R54
10 TX7
SDI SDI C24 2.55k
1 2 3 4 5 6 28 330pF 1W
SCK SDI 13 TX7
SDO 250V
GND
GND
VSS
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND

JTAG J3 TP39
TP17
57
54
17
44
25
46
47
26
27
24
45

R9
TP24
VCC VDD VSS VPP 1.0k
TP36 R52
VCC TP15
R30 C36 0
R31 R38 R35 1µ R32
1.0 2.55k
C30 1.0 1.0 1.0 C23
R25 R26 R27 R28 R29 VSS 330pF 1W
0.22
33k 33k 33k 33k 33k 250V TP33

TP37
VDD VCC VDD VPP VPP
R40 R41 R42 R43 R45 R53
1 2 3 4 5 6 D20A D20B D22A D22B D17 D15
200 200 200 200 200
0
HEADER 6 J4 6 3 6 3 1 1 R34
SW1 SW2 SW3 SW4 SW5 C37 2.55k
1 4 1 4 2 2 330pF 1W
VCC = +3.3V 250V TP38
C31 C32 C33 C34 C35
B1100-13
B1100-13

0.22 0.22 0.22 0.22 0.22 MH2 MH3 MH4 MH1

BAT54DW-7
BAT54DW-7
BAT54DW-7
BAT54DW-7

VDD/VSS = +/-5.0V
VSS VCC VDD
VPP = +5.0 to +150V

www.supertex.com
Supertex inc.
HV7355DB1
 HV7355DB1
HV7355DB1 PCB and Board Layout

Actual Board Size: 72.4mm x 68.4mm

Power Connector Description

1 VCC +3.3V Logic voltage input for VLL and CPLD. (100mA)
2 GND 0V, Ground
3 VDD +5.0V HV7355 positive VDD supply. (25mA)
4 VSS -5.0V HV7355 negative VSS supply. (-25mA)
5 GND 0V, Ground
6 VPP +10 to +150V positive high voltage supply. (5mA)

Voltage Supply Power-Up and Operation Sequence

1 +VCC +3.3V positive logic supply voltage for HV7355’s VLL and CPLD VCC.
2 +VDD / -VSS ±5.0V positive and negative VDD and VSS power supply.
3 +VPP +10 to +150V positive high voltage.
Note:
Power-down in reverse order

Push Button Operations

WAV Toggle select pulse B-mode waveforms: None, 1-cycle, 3-cycles, 7-cycles.
FREQ Toggle select frequency: 20, 10, 5, 2.5, 1.25 and 0.625MHz when X1 oscillator is 40MHz.
SEL Toggle select. Increases the off-time between 2 consecutive pulses.
EN Toggle ON or OFF HV7355 chip enable
MODE Toggle select between B-mode and CW.

LED Indicator
SET Set the latch registers of serial interface, when high, all latches are set to logic high.
LE Latch enable when low, data can be latched into the registers of serial interface.
MC Mode control, high indicates B-mode and low indicates CW.
PWR HV7355 VLL 3.3V and CPLD chip VCC power supply indicator.
EN HV7355 chip enable signal indicator. Power state initially is OFF until EN is pushed.

Doc.# DSDB-HV7355DB1
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Supertex inc.
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 HV7355DB1
Typical Waveforms

Figure 1. Input logic and TX output waveforms of 5.0MHz (0 to +150V with 330pF//2.5kΩ load)

Figure 2. Rise and fall time at 0 to +150V (with 330pF//2.5kΩ load)

Doc.# DSDB-HV7355DB1
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 HV7355DB1
Typical Waveforms (cont.)

Figure 3. Multiple channel at 5.0MHz (0 to +150V with 330pF//2.5kΩ load)

Figure 4. FFT Plot of Second Harmonic Distortion (HD2) -36dB at 5.0MHz,

VPP = 150V (with 330pF//2.5kΩ load)

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Supertex inc.
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 HV7355DB1
Typical Waveforms (cont.)

Figure 5. Output Waveform at 10MHz and VPP = 120V (with 330pF//2.5kΩ load)

Figure 6. Output Waveform at 2.5MHz and VPP = 120V (with 330pF//2.5kΩ load)

Doc.# DSDB-HV7355DB1
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 HV7355DB1
Typical Waveforms (cont.)

Figure 7. Output Waveform at 20MHz at VPP = 75V (with 330pF//2.5kΩ load)

Figure 8. Power on EN chip enable to VPF setting time

Doc.# DSDB-HV7355DB1
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Supertex inc.
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 HV7355DB1
Bill of Materials
Component Description Manufacturer Part Number
C1 - C3, C18, C19,
CAP CER 0.22µF 16V X7R 10% 0603 TDK C1608X7R1C224K
C22, C30 - C35
C4, C7, C20 - C24,
CAP CER 330pF 200V X7R 0603 Panasonic ECJ-1VB2D331K
C29, C37
C5, C8, C12, C13,
CAP CER 1.0µF 16V X7R 0603 TDK C1608X7R1C105M
C14, C36
C6, C9, C27, C28 CAP CER 1µF 100V X7R 20% 1210 TDK C3225X7R2A105M
D3, D7 LED THIN 635NM RED DIFF 0805 SMD Lumex SML-LXT0805IW-TR
D4, D5 LED THIN 585NM YEL DIFF 0805 SMD Lumex SML-LXT0805YW-TR
D6 LED THIN 565NM GRN DIFF 0805 SMD Lumex SML-LXT0805GW-TR
D15, D17 DIODE SCHOTTKY 100V 1A SMA Diodes Inc. B1100-13
D20, D22 DIODE SCHOTTKY DUAL 30V SOT-363 Diodes Inc. BAT54DW-7
J1 CONN HEADER 2POS .100 VERT GOLD Molex 22-28-4023
J2 CONN JACK END LAUNCH PCB GOLD SMA Johnson 142-0711-821
J3 CONN HEADER 6POS .100 VERT GOLD Molex 22-28-4063
J4 CONN HEADER 10POS .100 VERT GOLD Tyco 1-640454-0
R2, R10, R12, R18,
Solder Gap (SHORT) NA NA
R23, R37, R52, R53
R3, R11, R13, R19,
RES 2.55kΩ 1W 1% 2512 SMD Panasonic ERJ-1TNF2551U
R24, R32, R34, R54
R4, R5, R6, R7, R8,
RES 1.00kΩ 1/16W 1% 0603 SMD Panasonic ERJ-3EKF1001V
R9, R14
R15 - R17, R20 - R22,
R33, R36, R39, RES 49.9Ω 1/16W 1% 0603 SMD Panasonic ERJ-3EKF49R9V
R45 - R51
R25, R26, R27, R28,
RES 33.2kΩ 1/16W 1% 0603 SMD Panasonic ERJ-3EKF3322V
R29
R30, R31, R35, R38 RES 1.00Ω 1/10W 1% 0603 SMD Rohm MCR03EZPFL1R00
R40, R41, R42, R43,
RES 200Ω 1/16W 1% 0603 SMD Panasonic ERJ-3EKF2000V
R44
SW1, SW2, SW3,
SWITCH LT 4.7MMX3.5MM 100GF SMD Panasonic EVQ-P2002M
SW4, SW5
TP3, TP15 TEST POINT PC MULTI PURPOSE BLK Keystone 5011
U2 IC CPLD 72 MCELL C-TEMP 44-VQFP Xilinx XC9572XL-5VQ44C
U3 IC HV7355K6-G 4-ch RTZ Supertex Inc. HV7355K6-G
X1 OSC CLOCK 40.000MHz 3.3V SMD CTS CB3LV-3C-40.0000-T

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)

©2014 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Doc.# DSDB-HV7355DB1 Tel: 408-222-8888
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