FET Baising

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Introduction
• The nonlinear relationship between ID and VGS can complicate
the mathematical approach to the DC analysis of FET
configuration.
• Another distinct difference between the analysis of BJT and
FET transistors is that the input controlling variable for a BJT
transistor is a current level, while for the FET a voltage is the
controlling variable.
• In both cases, however, the controlled variable on the output
side is a current level that also defines the important voltage
levels of the output circuit

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Introduction
• In general relationships that can be applied to the DC analysis of all
FET amplifiers are.
and
• For JFET and depletion-type MOSFET:

• For enhancement-type MOSFET:

• Do not interchange the use of equation

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FIXED-BIAS CONFIGURATION 4

(JFET & D-MOSFET)

Fixed bias configuration
• The simplest of biasing arrangement for n-channel JFET.
• Since we are dealing with dc analysis, we can remove V i and
Vo and coupling capacitors.
• The zero-volt voltage drop across RG can be replaced by short-
circuit equivalent. IG ≈ 0A
VRG = IGRG = (0A)RG = 0V
VDD
VDD
RD RD
D
Vo
G IDSS
Vi C2
Vp
C1 S
RG VGG 5
VGG
Fixed bias configuration
• Applying Kirchhoff’s voltage law in the clockwise direction of the
indicated loop of the input circuit.
– VGG – VGS = 0
VGS = –VGG
• The resulting level of drain current ID is now controlled by
Shockley’s equation:

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Fixed bias configuration
• The drain-to-source voltage of the output circuit can
be determined by applying Kirchhoff’s voltage laws
as follows:
+VDS + IDRD – VDD = 0
VDS = VDD - IDRD
• Since VS = 0V
VDS = VD – VS
VD = VDS
also,
VGS = VG – VS 7

VG = VGS
Fixed bias: sample problem 1
• Determine the following for the network.
a) VGSQ
b) IDQ
c) VDS
d) VD
e) VG
f) VS

Note: Q means certain point on

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the characteristics of the device,
called quiescent point
Fixed bias: sample problem 1
a) VGSQ = _______ = -2V
b) IDQ = _______ = 5.625 mA
c) VDS = _______ = 4.75V
d) VD = _______
e) VG = _______
f) VS = _______

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SELF-BIAS CONFIGURATION 10

(JFET AND D-MOSFET)

Self-bias configuration
• The self-bias configuration eliminates the need for two DC
supplies.
• The controlling gate-to-source voltage is now determined
by the voltage across a resistor RS introduced in the source
leg of the configuration.
• For DC analysis, the capacitors can be removed and resistor
RG replaced by short-circuit since IG=0A.

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Self-bias configuration
• The current through RS is IS, but IS = ID
VRS = IDRS
• For the indicated closed loop:
– VGS – VRS = 0
VGS = – VRS = – IDRS
• A mathematical solution could be obtained by using
Shockley’s equation.

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• Note: one ID value is acceptable based on limitation of the device.
Self-bias configuration
• The level VDS can be determined by Kirchhoff’s
voltage law to the output circuit:
VDD – VRS – VDS – VRD = 0
VDS = VDD – VRS – VRD where: ID = IS
VDS = VDD – ID(RS +RD)
also,
V S = I DR S
VG = 0V
VD = VDS + VS = VDD – VRD 13
Self-bias: sample problem 2
• Determine the following for the network
a) IDQ
b) VGSQ +20V
c) VDS
d) VS 3.3kΩ
e) VG
f) VD
IDSS = 8mA
VP = -6V

1MΩ
RS 1kΩ
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Self-bias: sample problem 2
a) IDQ = _______ = 2.59mA
(Note: 13.91 mA exceeds IDSS)
b) VGSQ = _______ = –2.59V
c) VDS = _______ = 8.86V
d) VS = _______
e) VG = _______
f) VD = _______
(Note: Another way of solving this is through graphical approach
which will not be discussed in this lesson)

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VOLTAGE-DIVIDER BIAS CONFIGURATION 16

(JFET & D-MOSFET)

 Voltage-divider bias
configuration
• The voltage-divider bias arrangement applied to BJT transistor amplifier is
also applied to FET amplifier.
• IG = 0A for FET amplifier will not affect the output. VGS values have the link
between input and output for FET configuration.
• Capacitors can be removed for DC analysis.
• The source VDD can be separated to two equivalent sources of the input
and the output circuit.

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Voltage-divider bias
configuration
• Since IG = 0A, Kirchhoff’s current law shows I R1 = IR2.
• The voltage VG can be found using voltage divider rule.

• Applying Kirchhoff’s voltage law in the clockwise direction.

VG – VGS – VRS = 0
VGS = VG – IDRS
• Instead of VGS, we can use VG – IDRS in Shockley’s equation
and will result to quadratic equation where I D is the
unknown value. It is necessary to choose the appropriate
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root that will satisfy the device limitation.
Voltage-divider bias
configuration
• Once the equivalent values of IDQ and VGSQ are
determined, the remaining network can be
performed in the usual manner.

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Voltage-divider bias: sample
problem 3
• Determine the following for the network.
a) IDQ
b) VGSQ
c) VD
+16V
d) VS
e) VDS 2.4kΩ
f) VDG 2.1MΩ

IDSS = 8mA
VP = -4V
270kΩ
1.5kΩ
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Voltage-divider bias: sample
problem 3
a) IDQ = _______ = 2.4mA
(Note: VGS exceeds VP when 6.234 mA is substituted)
b) VGSQ = _______ = –1.8V
c) VD = _______ = 10.24V
d) VS = _______ = 3.6V
e) VDS = _______ = 6.64V
f) VDG = _______ = 8.42V

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Voltage-divider bias: sample
problem 4
• For n-channel depletion-type MOSFET,
determine: 18V
a) IDQ = ____ = 3.11mA
b) VSGQ = ____ = – 0.83V
1.8kΩ
c) VDS = ____ = 10.07V 110MΩ

IDSS = 6mA
VP = -3V

10MΩ
(Use Shockley’s equation) 750Ω
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VOLTAGE DIVIDER-BIAS 23

CONFIGURATION (E-MOSFET)
Enhancement-type MOSFET
• Enhancement-type MOSFET
• The transfer characteristics of the enhancement-type MOSFET
are quite different from those encountered for the JFET and
depletion-type MOSFETs, resulting in a graphical solution
quite different from the preceding sections.
• The transfer characteristic will have the equation:

• The constant k must be determine from the specification

sheet data:

• Once k is defined, other levels of ID can be determined for 24

chosen values of VGS.
Voltage-divider bias
configuration
• For the image, IG = 0mA results in the
VDD
following equation for input circuit.
RD
R1
• Applying Kirchhoff’s voltage law
around the indicated loop.
VG – VGS – VRS = 0
VGS
R2
• For the output circuit: RS

VRS + VDS + VRD – VDD = 0

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Voltage-divider bias: sample
problem 5
• Determine the IDQ, VGSQ and VDS with E-MOSFET network
below.
• IDQ = ____ = 6.72mA 40V

• VGSQ = ____ = 12.49V

• VDS = ____ = 14.33V 3kΩ
22MΩ IDQ
2N4351
VDS VGS(Th) = 5V
ID(on) = 3mA
VGS(on) = 10V
VGSQ
18MΩ
820Ω
(Note: use equation w/ constant k) 26
• There are few more configuration for FET. The fundamental
approach shown can also be use for more complex network.

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