FET Amplifiers

• Excellent voltage gain

• High input impedance
• Low-power consumption
• Good frequency range

Chapter 7: FET Biasing Chapter 8: FET Amplifiers

Using VGSQ to determine Step 2: AC analysis

Step 1: DC analysis gm for AC equivalent Based on AC network and
Based on DC network: model AC equivalent model:
• VGSQ
• Input impedance
• IDQ
• Output impedance
• VDSQ
• Voltage gain
Three basic configurations for FET amplifiers
CS: Common Source Configuration
CG: Common Gate Configuration
CD(Source Follower): Common Drain
 Chapter 7 FET Biasing
7.1 Introduction DC analysis methods: VGSQ, IDQ, VDSQ
Common FET Biasing Circuits
• Mathematical approach
JFET • Graphical approach
• Fixed-Bias General Relationships
• Self-Bias
• Voltage-Divider Bias For all FETs:

Depletion-Type MOSFET
•Self-Bias
For JFETS and depletion-type MOSFETs:
•Voltage-Divider Bias

Enhancement-Type MOSFET
•Feedback Configuration
For enhancement-type MOSFETs:
•Voltage-Divider Bias
 7.2 Fixed-Bias Configuration
 Mathematical Approach

 Graphical Approach
EXAMPLE 7.1 Determine the following for the network:
a. VGSQ. b. IDQ. c. VDS. d. VD. e. VG. f. VS.

Solution:
Mathematical Approach
Graphical Approach The resulting Shockley curve and the vertical line at VGS = -2V are provided in
the below figure. It is certainly difficult to read beyond the second place without significantly
increasing the size of the figure, but a solution of 5.6mA from the graph is quite acceptable.

The results clearly confirm the fact that the mathematical and
graphical approaches generate solutions that are quite close.
 7.3 Self-Bias Configuration
 Mathematical Approach

 Graphical Approach
 EXAMPLE 7.2 Determine the following for the network:
a. VGSQ. b. IDQ. c. VDS. d. VS. e. VG. f. VD.

Solution:

The result is plotted in the below figure as defined by the network.

EXAMPLE 7.3 Find the quiescent point for the network of Fig. 7.12 if :
a. RS = 100Ω.
b. RS = 10kΩ.
 7.4 Voltage-Divider Biasing
Mathematical Approach

Graphical Approach
EXAMPLE 7.5 Determine the following for the network :
a. IDQ and VGSQ. b. VD. c. VS. d. VDS. e. VDG.

Solution:
a. For the transfer characteristics, if ID = IDSS /4 = 8 mA/4
= 2 mA, then VGS =VP /2 = -4 V/2 = -2 V. The resulting
curve representing Shockley’s equation appears in Fig.
7.22. The network equation is defined by
 7.5 Depletion-Type MOSFETs
The similarities in appearance between the transfer curves of JFETs and depletion-type MOSFETs permit a
similar analysis of each in the dc domain. The primary difference between the two is the fact that depletion-
type MOSFETs permit operating points with positive values of VGS and levels of ID that exceed IDSS. In fact,
for all the configurations discussed thus far, the analysis is the same if the JFET is replaced by a depletion-
type MOSFET.
EXAMPLE 7.6 For the n-channel depletion-type MOSFET of the below figure, determine:
a. IDQ and VGSQ.
b. VDS.
hence

b.
EXAMPLE 7.8 Determine the following for the network of Fig. 7.33:
a. IDQ and VGSQ.
b. VD .
 7.6 Feedback Biasing for E-MOSFETs
Mathematical Approach Feedback Biasing
Arrangement

Graphical Approach
EXAMPLE 7.11 Determine IDQ and VDSQ for the enhancement-type MOSFET of the below figure.
Solution:
Plotting the Transfer Curve Two points are defined immediately
as shown in the below figure. Solving for k, we obtain
 Voltage-Divider
Biasing Arrangement

Since the characteristics are a plot of ID versus VDS relates the same two
variables, the two curves can be plotted on the same graph and a
solution determined at their intersection. Once IDQ and VGSQ are known,
all the remaining quantities of the network such as VDS, VD, and VS can
be determined.
EXAMPLE 7.12 Determine IDQ, VGSQ, and VDS for the network of the below figure.
Solution:
 SUMMARY
Important Conclusions and Concepts
1. A fixed-bias configuration has, as the label implies, a fixed dc voltage applied from gate to source to
establish the operating point.
2. The nonlinear relationship between the gate-to-source voltage and the drain current of a JFET requires
that a graphical or mathematical solution (involving the solution of two simultaneous equations) be used to
determine the quiescent point of operation.
3. All voltages with a single subscript define a voltage from a specified point to ground.
4. The self-bias configuration is determined by an equation for VGS that will always pass through the origin.
Any other point determined by the biasing equation will establish a straight line to represent the biasing
network.
5. For the voltage-divider biasing configuration, one can always assume that the gate current is 0A to permit
an isolation of the voltage-divider network from the output section. The resulting gate-to-ground voltage
will always be positive for an n–channel JFET and negative for a p-channel JFET. Increasing values of
RS result in lower quiescent values of ID and more negative values of VGS for an n-channel JFET.
 SUMMARY
6. The method of analysis applied to depletion-type MOSFETs is the same as applied to JFETs, with the
only difference being a possible operating point with an ID level above the IDSS value.

7. The characteristics and method of analysis applied to enhancement-type MOSFETs are entirely
different from those of JFETs and depletion-type MOSFETs. For values of VGS less than the threshold
value, the drain current is 0 A.

8. When analyzing networks with a variety of devices, first work with the region of the network that will
provide a voltage or current level using the basic relationships associated with those devices. Then use
that level and the appropriate equations to find other voltage or current levels of the network in the
surrounding region of the system.

9. The analysis of p-channel FETs is the same as that applied to n-channel FETs except for the fact that all
the voltages will have the opposite polarity and the currents the opposite direction.
 Chapter 8: FET Amplifiers

CHAPTER OBJECTIVES
•Become acquainted with the small-signal ac model for a JFET and MOSFET.
•Be able to perform a small-signal ac analysis of a variety of JFET and MOSFET
configurations.
•Begin to appreciate the design sequence applied to FET configurations.
•Understand the effects of a source resistor and load resistor on the input
impedance, output impedance and overall gain.
•Be able to analyze cascaded configurations with FETs and/or BJT amplifiers.
 8.1 Introduction
Field-effect transistor amplifiers provide an excellent voltage gain with the added feature of a high input
impedance. They are also low-power-consumption configurations with good frequency range and minimal
size and weight. JFETs, depletion MOSFETs, and MESFETs can be used to design amplifiers having
similar voltage gains. The depletion MOSFET (MESFET) circuit, however, has a much higher input
impedance than a similar JFET configuration.

Whereas a BJT device controls a large output (collector) current by means of a relatively small input
(base) current, the FET device controls an output (drain) current by means of a small input (gate-voltage)
voltage. In general, therefore, the BJT is a current-controlled device and the FET is a voltage-controlled
device. In both cases, however, note that the output current is the controlled variable. Because of the high
input characteristic of FETs, the ac equivalent model is somewhat simpler than that employed for BJTs.
Whereas the BJT has an amplification factor, β (beta), the FET has a transconductance factor, gm .
 8.2 FET Small-Signal Model
Transconductance
The relationship of VGS(input) to ID(output) is called transconductance denoted
by gm.
Mathematical Determinations of gm Graphical Determination of gm

Where VGS =0V

Where

With a small signal input, FET acts as a linear device:

EXAMPLE 8.1 Determine the magnitude of gm for a JFET with IDSS=8mA and VP=-4V at the following dc bias
points: a. VGS=-0.5 V. b. VGS=-1.5 V. c. VGS= -2.5 V.

Solution: The transfer characteristics are generated

as Fig. 8.2 using the procedure defined in Chapter 7.
Each operating point is then identified and a tangent
line is drawn at each point to best reflect the slope
of the transfer curve in this region. An appropriate
increment is then chosen for V G S to reflect a
variation to either side of each Q-point.
 FET Impedance FET AC Equivalent Circuit
Input impedance:

Output Impedance:

where:

yos= admittance equivalent circuit parameter

listed on FET specification sheets.
EXAMPLE 8.5 Determine the output impedance for the JFET of the below figure for VGS = 0V and
VGS = -2V at VDS = 8V.

Solution: For VGS=0V, a tangent line is

d r a w n a n d V D S i s c h o s e n a s 5 V,
resulting in a ID of 0.2 mA. We find:

For VGS=-2V, a tangent line is drawn and VDS is chosen as 8V, resulting in a ID of 0.1 mA

which shows that rd does change from one operating region to another, with lower values typically
occurring at lower levels of VGS (closer to 0 V).
JFET ac equivalent model
8.3 JFET Common-Source (CS) Fixed-Bias Configuration
The input is on the gate and the output is on the
drain
Input impedance:

Output impedance:

Voltage gain:

CS: There is a 180 phase shift between input and

EXAMPLE 8.7 The fixed-bias configuration of Example 7.1 had an operating point defined by VGSQ=-2V
and IDQ=5.625mA, with IDSS=10mA and VP=-8V. The network is redrawn as Fig. 8.14 with an applied
signal Vi. The value of yos is provided as 40mS.
a. Determine gm. b. Find rd.
c. Determine Zi. d. Calculate Zo.
e. Determine the voltage gain Av.
f. Determine Av ignoring the effects of rd.
Solution:

As demonstrated in part (f), a ratio of 25kΩ:2kΩ = 12.5:1 between rd and RD results in a difference of
8% in the solution.
 8.4 JFET Common-Source Self-Bias Configuration
The input is on the gate and the
output is on the drain

Input impedance:

Output impedance:

Voltage gain:
 8.4 JFET Common-Source Self-Bias Configuration
Removing Cs affects the gain of the
circuit.
Input impedance:

Output impedance:

Voltage gain:
 8.5 JFET CS Voltage-Divider Configuration
The input is on the gate and the output is on the drain.

Input impedance:

Output impedance:

Voltage gain:
8.6 JFET Source Follower (Common-Drain) Configuration
In a common-drain amplifier configuration, the
input is on the gate, but the output is from the
source.
There is no phase shift between input and
output.
Input impedance:

Output impedance:

Voltage gain:
EXAMPLE 8.10 A dc analysis of the source-follower network of Fig. 8.28 results in VGSQ =-2.86V and
IDQ=4.56mA.
a. Determine gm. b. Find rd. c. Determine Zi.
d. Calculate Zo with and without rd. Compare results.
e. Determine Av with and without rd. Compare results.
 8.7 JFET Common-Gate Configuration
The input is on the source and the output is on the
drain.
Input impedance:

Output impedance:

Voltage gain:

There is no phase shift between input and

EXAMPLE 8.10 Although the network of Fig. 8.27 may not initially appear to be of the common-gate
variety, a close examination will reveal that it has all the characteristics of Fig. 8.24 . If VGSQ = -2.2 V
and IDQ = 2.03 mA:
a. Determine gm. b. Find rd.
c. Calculate Zi with and without rd . Compare results.
d. Find Zo with and without rd . Compare results.
e. Determine Vo with and without rd . Compare results.
Even though the condition rd≥10RD is not satisfied with rd=20kΩ and 10RD=36 kΩ, both equations
result in essentially the same level of impedance. In this case, 1/gm was the predominant factor.
 8.8 Depletion-Type MOSFETs
• D-MOSFETs have the same AC equivalent model and same equation for gm with JFETs .
• The only difference is that VGSQ can be positive for n-channel devices and negative for p-
channel devices. This means that gm can be greater than gm0.

8.9 Enhancement-Type MOSFETs

• E-MOSFETs have the similar AC equivalent model
with JFETs
• Equation for gm is different.
Transfer equation for E-MOSFETs:
EXAMPLE 8.11 VGSQ=0.35V and IDQ=7.6mA.
a. Determine gm and compare to gm0. b. Find rd.
c. Sketch the ac equivalent network for Fig. 8.34.
d. Find Zi. e. Calculate Zo. f. Find Av.
 8.10 E-MOSFET CS Drain-Feedback Configuration
There is a 180 phase shift between input and output for CS
amplifiers.
Input impedance:

Output impedance:

Voltage gain:
EXAMPLE 8.12 The E-MOSFET was analyzed, with the result that k=0.24*10-3 A/V2, VGSQ=6.4V, and
IDQ=2.75 mA.
a. Determine gm. b. Find rd.
c. Calculate Zi with and without rd. Compare results.
d. Find Zo with and without rd. Compare results.
e. Find Av with and without rd. Compare results.
 8.11 E-MOSFET CS Voltage-Divider Configuration

Input impedance:

Output impedance:

Voltage gain:
8.12 Summary Table

8.13 Effect of RL and RS Note: Methods and conclusions are the same
with that for BJT amplifiers in 5.16, 5.19.
8.14 Cascade
Configuration
 Summary of FET Amplifiers
 Comparisons of FETs and BJTs
• Voltage controlled
• High input impedance
• Less sensitive to temperature
• Low power consumption

 FET Amplifiers
• Analysis methods are same for FET amplifiers
and BJT amplifiers except their specific
characteristics and small-signal model
• DC and AC analysis
• cascaded systems
• CS, CG, CD
 Important Conclusions and Concepts
1. The transconductance parameter gm is determined by the ratio of the change in drain current
associated with a particular change in gate-to-source voltage in the region of interest. The steeper the
slope of the ID-versus-VGS curve, the greater is the level of gm . In addition, the closer the point or
region of interest to the saturation current IDSS , the greater is the transconductance parameter.

2. On specification sheets, gm is provided as yfs.

3. When VGS is one-half the pinch-off value, gm is one-half the maximum value.

4. When ID is one-fourth the saturation level of IDSS, gm is one-half the value at saturation.

5. The output impedance of FETs is similar in magnitude to that of conventional BJTs.

6. On specification sheets the output impedance r d is provided as 1/y os . The more horizontal the
characteristic curves on the drain characteristics, the greater is the output impedance.
7. The voltage gain for the fixed-bias and self-bias JFET configurations is the same.

8. The ac analysis of JFETs and depletion-type MOSFETs is the same.

9. The ac equivalent network for an enhancement-type MOSFET is the same as that employed for JFETs
and depletion-type MOSFETs. The only difference is the equation for gm.

10. The magnitude of the gain of FET networks is typically between 2 and 20. The selfbias
configuration (without a bypass source capacitance) and the source-follower are low-gain configurations.

11. There is no phase shift between input and output for the source-follower and commongate
configurations . Most others have a 180° phase shift.

12. The output impedance for most FET configurations is determined primarily by RD. For the source-
follower configuration it is determined by RS and gm.

13. The input impedance for most FET configurations is quite high. However, it is quite low for the
common-gate configuration.