Sana’a University Mechatronics

Faculty of Engineering Department

Analog Electronics
Experiment :
Field Effect Transistor (FET)

Dr. abdulkafi
En. Lamis

Done by: Ahmed saleh saleh Al-Hithani

202070225
nd
2 Year Mechatronics General
Table of Contents
Abstract .................................................................................................................. 1

Objectives ............................................................................................................... 2

Procedure ............................................................................................................... 6

Results .................................................................................................................... 7

Table 1. Output data................................................................................................ 7

Discussion ............................................................................................................... 9

Conclusion and Recommendation ............................................................................ 9

References .............................................................................................................. 9

Abstract
We are going to learn about an experiment to find out the Junction Field
Effect Transistor Characteristics and understand the basic characteristics of
JFETs.

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Objectives
• To understand the basic characteristics of JFETs.
• To put JFET in comparison with BJT according to the graph
of the result.
• To Draw the drain and transfer characteristics of a given FET.

Introduction
The acronym ‘FET’ stands for field effect transistor. It is a three-terminal
unipolar solid-state device in which current is controlled by an electric field
as is done in vacuum tubes.
Broadly speaking, there are two types of
FETs : (a) junction field effect transistor
(JFET)
(b) metal-oxide semiconductor FET (MOSFET)
It is also called insulated-gate FET (IGFET). It may be further subdivided
into :
(i) depletion-enhancement MOSFET i.e.
DEMOSFET (ii) enhancement-only MOSFET
i.e. E-only MOSFET Both of these can be
either P-channel or N-channel devices.
The FET family tree is shown below :

As shown in Fig.1, it can be fabricated with either an N-channel or P-

channel though Nchannel is generally preferred. For fabricating an N-
channel JFET, first a narrow bar of Ntype semiconductor material is taken

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and then two P-type junctions are diffused on opposite sides of its middle
part [Fig.1 (a)]. These junctions form two P-N diodes or gates and the area
between these gates is called channel. The two P-regions are internally
connected and a single lead is brought out which is called gate terminal.
Ohmic contacts (direct electrical connections) are made at the two ends of
the bar-one lead is called source terminal S and the other drain terminal D.
When potential difference is established between drain and source, current
flows along the length of the ‘bar’ through the channel located between the
two Pregions. The current consists of only majority carriers which, in the
present case, are electrons. P-channel JFET is similar in construction except
that it uses P-type bar and two Ntype junctions. The majority carriers are
holes which flow through the channel located between the two N-regions
or gates.
Following FET notation is worth remembering:
1. Source. It is the terminal through which majority carriers enter the bar.
Since carriers come from it, it is called the source.
2. Drain. It is the terminal through which majority carriers leave the bar i.e.
they are drained out from this terminal. The drain to source voltage V DS
drives the drain current ID.
3. Gate. These are two internally-connected heavily-doped impurity regions
which form two P-N junctions. The gate-source voltage VGS reverse biases
the gates.
4. Channel. It is the space between two gates through which majority carriers
pass from source-to-drain when VDS is applied.
Schematic symbols for N-channel and P-channel JFET are shown in Fig.1
(c). It must be kept in mind that gate arrow always points to N-type
material.

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 Fig. 1 FET construction
Static Characteristics of a JFET
We will consider the following two characteristics:
(i) drain characteristic: It gives relation between ID and VDS for different
values of VGS (which is called running variable).
(ii) transfer characteristic: It gives relation between ID and VGS for
different values of VDS. We will analyze these characteristics for an N-
channel JFET connected in the common-source mode as shown in Fig. 2.
We will first consider the drain characteristic when VGS= 0 and then when
VGS has any negative value upto VGS(off).

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 Fig. 2

JFET Drain Characteristic With VGS = 0

Such a characteristic is shown in Fig. 3.
It can be subdivided into following four regions :
1. Ohmic Region OA: This part of the characteristic is linear indicating
that for low values of VDS, current varies directly with voltage following
Ohm's Law. It means that JFET behaves like an ordinary resistor till point A
(called knee) is reached.
2. Curve AB In this region, ID increases at reverse square-law rate upto
point B which is called pinch-off point. This progressive decrease in the rate
of increase of ID is caused by the square law increase in the depletion region
at each gate upto point B where the two regions are closest without touching
each other.

Fig. 3

3. Pinch-off Region BC: It is also known as saturation region or

‘amplified’ region. Here, JFET operates as a constant-current device because
ID is relatively independent of VDS. It is due to the fact that as VDS increases,

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channel resistance also increases proportionally thereby keeping ID
practically constant at IDSS. It should also be noted that the reverse bias
required by the gate-channel junction is supplied entirely by the voltage drop
across the channel resistance due to flow of IDSS and none by external bias
because VGS = 0.
4. Breakdown Region: If VDS is increased beyond its value
corresponding to point C (called avalanche breakdown voltage), JFET enters
the breakdown region where ID increases to an excessive value. This happens
because the reverse-biased gate-channel P-N junction undergoes avalanche
breakdown when small changes in VDS produce very large changes in ID. It
is interesting to note that increasing values of VDS make a JFET behave first
as a resistor (ohmic region), then as a constant-current source (pinch-off
region) and finally, as a constantvoltage source (breakdown region).

.Methodology
Analog trainer
Analog multimeter
Digital multimeter
1 2N5458
1 100 ohm resistor
1 5k potentiometer
Wires

Procedure
1. The circuit in figure was constructed using a 2N5458 JFET.
2. The VGG (Voltage source for the Gate) was adjusted until a VGS
(Gates to Source voltage) of -4V was achieved as a starting voltage
input.
3. The value of VDD
(Voltage source for the
Drain) was adjusted until a
VDS (Drain to Source
voltage) of 0.25V was
obtained.

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 4. The voltage across RD (Drain resistor) was measured and divided
by 100 and the ID(drain current) was acquired upon computing and
was then recorded. ID= VRD/100

5. Steps 2-4 were repeated until desired data were obtained.

6. For the VGS value of 0.25V and 0.5V, the VGG value was changed
to +5V and was connected to a 5k potentiometer where the voltage
was divided and the potentiometer was adjusted until desired value
was achieved. (As seen below)

Results
Table 1. Output data
VGS=-4V VGS=-3V VGS=-2V VGS=-1V VGS=0 VGS=0.25V VGS=0.5V
VDS
ID (A) ID (μA) ID (μA) ID (mA) ID (mA) ID (mA) ID (mA)
0.25 V 0 0 237 0.445 0.639 0.676 0.744
0.5 V 0 1 423 0.822 1.163 1.3 1.349
0.75 V 0 3 560 1.283 1.714 1.86 1.97
1.0 V 0 0 643 1.523 2.234 2.53 2.612
2.0 V 0 0 674 2.305 3.811 4.35 4.67
3.0 V 0 4 719 2.461 4.79 5.32 6.11
4.0 V 0 8 672 2.685 5.05 5.88 6.69
5.0 V 0 0 659 2.77 5.19 6.07 6.97
6.0 V 0 0 746 2.585 5.17 6.14 7.08
7.0 V 0 2 734 2.823 5.21 6.17 7.1
8.0 V 0 5 708 2.531 5.22 6.19 7.1
9.0 V 0 0 758 2.89 5.22 6.19 7.12
10 V 0 0 838 2.65 5.30 6.2 7.12
11 V 0 0 719 2.587 5.3 6.19 7.1
12 V 0 0 711 2.562 5.21 6.18 7.08

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Discussion
The value of ID where VGS is -4V and -3V is almost zero for the reason
that the pinch-off region of a JFET is somewhere below -4V where ID‘s
value should indeed be zero and increasing when VGS>-4V. These minute
discrepancy might be due to external factors like systematic errors, faulty
calibration, instruments or materials or random error, unpredictable
variations.

Conclusion and Recommendation

Basing on the results, graphs and the manner that these were obtained, it can
be concluded that a JFET.
is voltage controlled. This is for the reason that in order to vary the output of
the transistor the input voltages are the ones controlled and adjusted while
comparing it on how a BJT’s output is achieved where the input voltage stays
the same but the resistance in the base (assuming a Common Emitter
Configuration) varies. The graphs also show a considerable difference of the
curve of the two types of transistors under comparison where JFET’s curve
gradually became horizontal while BJT’s curve abruptly approached a slope
of zero. Therefore, a JFET has a very high input resistance where it will take
a reasonable change in input to change the output.

References
1. https://en.wikipedia.org/wiki/Diode
2. Robert L. Boylestad, Eleventh Edition, Electronic Devices and
Circuit Theory.