EXPERIMENT -03

FET CHARACTERISTICS
OBJECT:- To study the characteristics of field effect transistor and plot the static drain
characteristics of FET.
1. Drain current V/S Drain voltage characteristics for different fixed values of VGs.
2. Drain current V/S Drain voltage characteristics for different fixed values of VDs.

APPARATUS REQUIRED:- Trainer Kit(Current meter,Voltage meter,One FET),

Patch cords, Multimeter

THEORY:- The field effect transistor is emerging as an important member of the

semiconductor family .Today the junction FET(JFET) and insulated gate fet (IGFET) or
metal oxide semiconductor fet (MOSFET) are rapidly replacing both vacuum tubes and
the junction transistors in applications requiring high input impedance. The advantages
FETs have over the vacuum tubes used earlier are their smaller size , low power
consumption and lack of filament. The advantages of FETs over junction transistors are
that they have high input impedance and high power gain. FETs are comparatively easier
to fabricate. Also their fabrication process is particularly suited to make IC. The FET
differs from the conventional junction transistor in that its operation depends on the flow
of majority carriers only. That is why it is sometimes called a unipolar transistor. The
three terminals of a FET are 1.Source 2.Gate 3. Drain correspond respectively to the
Emitter, Base, and Collector of an ordinary transistor. “N-channel” and “P-channel”
versions of FET are available corresponding to NPN and PNP transistor as shown in Fig.
Source and Drain are usually interchangeable. The FET works on the Principle that the
thickness and hence the resistance of a conducting channel of a semiconducting material,
can be modulated or regulated by the magnitude of a potential applied to the input
terminals. The other solid state devices FET can be connected in three basic configuration
viz (1) Common Source (2) Common Gate (3) Common Drain configuration as shown in
fig. In the first configuration phase shift occurs between input and output where as in the
other two their exists no phase shift.

SOME IMPORTANT TERMINOLOGY REGARDING A JFET

SOURCE
The source is the terminal through which the majority carriers (electrons in case of
N-channel FET and holes in case of P-channel FET) enter the bar.

DRAIN
The drain is the terminal through which the majority carriers leave the bar.

GATE
On both sides of the N-channel bar, heavily doped P regions are formed. These
regions are called gates. Usually the two gates are joined together to from a single gate.
CHANNEL
The region between the source and drain, sandwiched between the two gates, is
called channel. The majority carriers move from source to drain through this channel.

JFET CHARACTERISTICS
As a BJT has static collector characteristics, so does a JFET have static drain
characteristics. Such characteristics are shown in fig. For each curve, the gate to source
voltage VGs=0. When VDs is zero, the channel is entirely open. But the drain current is
zero, because the drain terminal does not have any attractive force for the majority
carriers. For small applied voltage VDs, the bar acts as a simple resistor. Current ID
increases linearly with voltage VDs. This region (to the left of point A) of the curve is
called ohmic region, because the bar acts as an ohmic resistor. Ohmic voltage drop is
caused in the bar due to the flow of current ID. This voltage drop alonge the length of the
channel reverse biases the gate junction. The reverse biasing of the gate junction is not
uniform throughout. The reverse bias is more at the drain end then at the source end of
the channel. So, as we start increasing VDs, the channel starts constricting more at the
drain end. The channel is eventually pinched off. The current ID no longer increases with
the increase in VDs. It approaches a constant saturation value. The voltage VDs at which
the channel is “pinched off”(that is all the free charges from the channel are removed) is
called pinch-off voltage VD. The region of the from the channel are removed is called
pinch-off voltage VD. The region of the curve to the right of a point A is called pinch-
off region. A special significance is attached to the drain current in the pitch-off region
when VDs=0. It is given the symbol IDss. It signifies the drain current at pinch-off, when
the gate is shorted to the source. It is measured well in to the pinch-off region. In this case
IDss=7.4mA. When further increase in voltage VDs increase the reverse bias across the
gate junction. Eventually at high VDs, break down of the gate junction occurs. The drain
current ID shoots to a high value. Of course, when we use a JFET in a circuit, we avoid
the gate junction breakdown. If the gate reverse bias is increased (say VGs = -1 V.),the
curve shifts downward. The pinch-off occurs for smaller value of VDs. The maximum
saturation drain current is also smaller, because the conducting channel now becomes
narrower. For an increased reverse bias at the gate, the avlanch breakdown of the gate
junction occure at lower value of VDs. This happens because the effective bias at the gate
junction (at the drain end) is the voltage VGs---------voltage VDs. The greater the value of
VGs, the lower the value of VDs required for the junction to breakdown.

PROCEDURE:- Plot the static drain characteristics of FET.

(A). Drain current V/S Drain voltage characteristics for different value of VGs.
1. Make the circuit as shown is fig. Rotate VGs the knob on the left side of the panel
to the extreme anticlockwise direction.
2. Connect the main lead to the nearest main socket carrying 230V. A.C. 50 Hz.
3. Keep the power on/off switch to ‘ON’ position. The jewel light on the left hand
will glow.
 4. Increase the drain voltage VDs by rotating the knob in clockwise direction, in
suitable steps in say 1 volt. Note down the corresponding drain current (ID).
5. Now change VGs in suitable steps from -1v to -2v, -3v & -4v etc. and repeat the
above step (4) in Exp. No. 2(A).

(B). Drain current V/S Gate bias ( mutual or transfer ) characteristics for different fixed
values of VDs.
1. Make the circuit as shown in fig. Keep the drain voltage (VDs) is fixed to some
value say 1V.
2. Now change the gate bias (VGs) from -0.5v to -1v, -1.5v, -2v etc. and note down
the corresponding drain current.
3. Now change VDs in suitable steps from 20v. to 1v. i.e.(20v,16v,12v,8v,4v) and
repeat the above step(2) in Exp.no.2(B).

NOTE:- Do not increase the gate to source voltage beyond -5v.

OBSERVATION:-
1. Type number of the FET = BFW – 10.
2. Information from the data books.
(i) Maximum drain current rating = ____________mA.
(ii) Maximum drain voltage rating = ____________V.
3. Table for ID verses VDs for different fixed values of VGs.
4. Table for ID verses VGs for different fixed value of VDs.

TABLE – 1

Drain current ID(in mA)

S.No. VDs(inV.) VGs=0 VGs=-1v VGs=-2v VGs=-3v VGS=-4v

1.
2.
3.
4.
5.
6.
 TABLE -2

Drain current ID (in mA)

S.No. VGs(inV.) VDs=20V VDs=16V VDs=12V VDs=8V VDS=4v VDs=3v VDs=2v VDs=1v

1.
2.
3.
4.
5.
6.

CALCULATIONS:-

A Suitable operating point is selected , say at VDs=4v, VGs=-2v. At this operating point,
the parameters are calculated as follow:

∆VDs |
1. rd = ------------- | VGs= -2v =___________ =___________ KΩ
∆IDs |

∆ID |
2. Gm = ------------- | VDs= 4v =___________ =___________ mS
∆VGs |

∆VDs |
3. µ = ------------- | ID= ___mA =___________ =___________
∆VGs |
RESULT:-
1. The drain characteristics of the FET are plotted on the graph.
2. The parameters of FET determined from the drain characteristics are given blow.

S.No. Parameter Value Determined

1. rd ----------KΩ
2. Gm ----------mS
3. µ ---------