FET Amplifiers

8
CHAPTER OBJECTIVES
●
● Become acquainted with the small-signal ac model for a JFET and MOSFET.
● Be able to perform a small-signal ac analysis of a variety of JFET and MOSFET
configurations.
● Begin to appreciate the design sequence applied to FET configurations.
● Understand the effects of a source resistor and load resistor on the input impedance,
output impedance and overall gain.
● Be able to analyze cascaded configurations with FETs and/or BJT amplifiers.

8.1 INTRODUCTION
●
Field-effect transistor amplifiers provide an excellent voltage gain with the added feature
of a high input impedance. They are also low-power-consumption configurations with
good frequency range and minimal size and weight. JFETs, depletion MOSFETs, and
MESFETs can be used to design amplifiers having similar voltage gains. The depletion
MOSFET (MESFET) circuit, however, has a much higher input impedance than a similar
JFET configuration.
Whereas a BJT device controls a large output (collector) current by means of a relatively
small input (base) current, the FET device controls an output (drain) current by means of
a small input (gate-voltage) voltage. In general, therefore, the BJT is a current-controlled
device and the FET is a voltage-controlled device. In both cases, however, note that the
output current is the controlled variable. Because of the high input characteristic of FETs,
the ac equivalent model is somewhat simpler than that employed for BJTs. Whereas the BJT
has an amplification factor, b (beta), the FET has a transconductance factor, gm.
The FET can be used as a linear amplifier or as a digital device in logic circuits. In
fact, the enhancement MOSFET is quite popular in digital circuitry, especially in CMOS
circuits that require very low power consumption. FET devices are also widely used in
high-frequency applications and in buffering (interfacing) applications. Table 8.1 in Sec-
tion 8.13 provides a summary of FET small-signal amplifier circuits and related formulas.
Although the common-source configuration is the most popular one, providing an in-
verted, amplified signal, one also finds common-drain (source-follower) circuits providing
unity gain with no inversion and common-gate circuits providing gain with no inversion. As
with BJT amplifiers, the important circuit features described in this chapter include voltage
gain, input impedance, and output impedance. Due to the very high input impedance, the
input current is generally assumed to be 0 mA and the current gain is an undefined quantity.

481
482 FET AMPLIFIERS Whereas the voltage gain of an FET amplifier is generally less than that obtained using a
BJT amplifier, the FET amplifier provides a much higher input impedance than that of a
BJT configuration. Output impedance values are comparable for both BJT and FET circuits.
FET ac amplifier networks can also be analyzed using computer software. Using PSpice
or Multisim, one can perform a dc analysis to obtain the circuit bias conditions and an ac
analysis to determine the small-signal voltage gain. Using PSpice transistor models, one can
analyze the circuit using specific transistor models. On the other hand, one can develop a
program using a language such as C that can perform both the dc and ac analyses and
provide the results in a very special format.

8.2 JFET SMALL-SIGNAL MODEL

●
The ac analysis of a JFET configuration requires that a small-signal ac model for the JFET
be developed. A major component of the ac model will reflect the fact that an ac voltage
applied to the input gate-to-source terminals will control the level of current from drain to
source.
The gate-to-source voltage controls the drain-to-source (channel) current of a JFET.
Recall from Chapter 7 that a dc gate-to-source voltage controls the level of dc drain
current through a relationship known as Shockley’s equation: ID = IDSS (1 - VGS >VP)2.
The change in drain current that will result from a change in gate-to-source voltage can be
determined using the transconductance factor gm in the following manner:

ID = gm VGS (8.1)

The prefix trans- in the terminology applied to gm reveals that it establishes a relation-
ship between an output and an input quantity. The root word conductance was chosen
because gm is determined by a current-to-voltage ratio similar to the ratio that defines the
conductance of a resistor, G = 1>R = I>V.
Solving for gm in Eq. (8.1), we have

ID
gm = (8.2)
VGS

Graphical Determination of gm
If we now examine the transfer characteristics of Fig. 8.1, we find that gm is actually the
slope of the characteristics at the point of operation. That is,

y ID
gm = m = = (8.3)
x VGS

ID

IDSS
ΔID
gm ≡ (= Slope at Q-point)
ΔVGS

Q-point ΔID

ΔVGS

VP 0 VGS

FIG. 8.1
Definition of gm using transfer characteristic.
 Following the curvature of the transfer characteristics, it is reasonably clear that the JFET SMALL-SIGNAL 483
slope and, therefore, gm increase as we progress from VP to IDSS. In other words, as VGS MODEL
approaches 0 V, the magnitude of gm increases.
Equation (8.2) reveals that gm can be determined at any Q-point on the transfer charac-
teristics by simply choosing a finite increment in VGS (or in ID) about the Q-point and then
finding the corresponding change in ID (or VGS, respectively). The resulting changes in each
quantity are then substituted in Eq. (8.2) to determine gm.

EXAMPLE 8.1 Determine the magnitude of gm for a JFET with IDSS = 8 mA and
VP = -4 Vat the following dc bias points:
a. VGS = -0.5 V.
b. VGS = -1.5 V.
c. VGS = -2.5 V.

Solution: The transfer characteristics are generated as Fig. 8.2 using the procedure
defined in Chapter 7. Each operating point is then identified and a tangent line is drawn at
each point to best reflect the slope of the transfer curve in this region. An appropriate
increment is then chosen for VGS to reflect a variation to either side of each Q-point. Equa-
tion (8.2) is then applied to determine gm.
ID 2.1 mA
a. gm = ⬵ = 3.5 mS
VGS 0.6 V
ID 1.8 mA
b. gm = ⬵ ⬵ 2.57 mS
VGS 0.7 V
ID 1.5 mA
c. gm = = = 1.5 mS
VGS 1.0 V
Note the decrease in gm as VGS approaches VP. I (mA) D

7
gm at − 0.5 V 6 2.1 mA

(
ID = 8 mA 1 −
VGS
−4 V
) 2
5
0.6 V 4
gm at −1.5 V 1.8 mA 3

2
gm at −2.5 V 0.7 V
1.5 mA 1

−4 −3 −2 −1 0 VGS (V)
VP
1.0 V

FIG. 8.2
Calculating gm at various bias points.

Mathematical Definition of gm
The graphical procedure just described is limited by the accuracy of the transfer plot and
the care with which the changes in each quantity can be determined. Naturally, the larger
the graph, the better is the accuracy, but this can then become a cumbersome problem. An
alternative approach to determining gm employs the approach used to find the ac resistance
of a diode in Chapter 1, where it was stated that:
The derivative of a function at a point is equal to the slope of the tangent line drawn at
that point.
484 FET AMPLIFIERS If we therefore take the derivative of ID with respect to VGS (differential calculus) using
Shockley’s equation, we can derive an equation for gm as follows:
dID d VGS 2
gm = ` = c IDSS a 1 - b d
dVGS Q@pt. dVGS VP
d VGS 2 VGS d VGS
= IDSS a1 - b = 2IDSS c 1 - d a1 - b
dVGS VP VP dVGS VP
VGS d 1 dVGS VGS 1
= 2IDSS c 1 - dc (1) - d = 2IDSS c 1 - d c0 - d
VP dVGS VP dVGS VP VP
and

2IDSS VGS
gm = c1 - d (8.4)
0 VP 0 VP

where 0 VP 0 denotes magnitude only, to ensure a positive value for gm.

It was mentioned earlier that the slope of the transfer curve is a maximum at VGS = 0 V.
Plugging in VGS = 0 V into Eq. (8.4) results in the following equation for the maximum
value of gm for a JFET in which IDSS and VP have been specified:
2IDSS 0
gm = c1 - d
0 VP 0 VP

2IDSS
and gm0 = (8.5)
0 VP 0

where the added subscript 0 reminds us that it is the value of gm when VGS = 0 V. Equa-
tion (8.4) then becomes

VGS
gm = gm0 c 1 - d (8.6)
VP

EXAMPLE 8.2 For the JFET having the transfer characteristics of Example 8.1:
a. Find the maximum value of gm.
b. Find the value of gm at each operating point of Example 8.1 using Eq. (8.6) and com-
pare with the graphical results.

Solution:
2IDSS 2(8 mA)
a. gm0 = = = 4 mS (maximum possible value of gm)
0 VP 0 4V
b. At VGS = -0.5 V,
VGS -0.5 V
gm = gm0 c 1 - d = 4 mS c 1 - d = 3.5 mS (vs. 3.5 mS
VP -4 V graphically)
At VGS = -1.5 V,
VGS -1.5 V
gm = gm0 c 1 - d = 4 mS c 1 - d = 2.5 mS (vs. 2.57 mS
VP -4 V graphically)
At VGS = -2.5 V,
VGS -2.5 V
gm = gm0 c 1 - d = 4 mS c 1 - d = 1.5 mS (vs. 1.5 mS
VP -4 V graphically)

The results of Example 8.2 are certainly sufficiently close to validate Eq. (8.4) through
(8.6) for future use when gm is required.
 On specification sheets, gm is often provided as gfs or yfs, where y indicates it is part JFET SMALL-SIGNAL 485
of an admittance equivalent circuit. The f signifies forward transfer conductance, and the MODEL
s indicates that it is connected to the source terminal.
In equation form,

gm = gfs = yfs (8.7)

For the JFET of Fig. 6.20, gfs ranges from 1000 mS to 5000 mS, or 1 mS to 5 mS.

Plotting gm versus VGS

VGS
Since the factor a 1 - b of Eq. (8.6) is less than 1 for any value of VGS other than 0 V,
VP VGS
the magnitude of gm will decrease as VGS approaches VP and the ratio increases in
VP
magnitude. At VGS = VP, gm = gm0 (1 - 1) = 0. Equation (8.6) defines a straight line
with a minimum value of 0 and a maximum value of gm, as shown by the plot of Fig. 8.3.
In general, therefore
the maximum value of gm occurs where VGS ⴝ 0 V and the minimum value at
VGS ⴝ VP. The more negative the value of VGS the less the value of gm.
Figure 8.3 also shows that when VGS is one-half the pinch-off value, gm is one-half the
maximum value.
gm (S)

gm 0

gm0
2

VP VP 0 VGS (V)
2

FIG. 8.3
Plot of gm versus VGS.

EXAMPLE 8.3 Plot gm versus VGS for the JFET of Examples 8.1 and 8.2.
Solution: Note Fig. 8.4. gm (S)

4 mS

2 mS

−4 V −2 V 0 VGS (V)

FIG. 8.4
Plot of gm versus VGS for a JFET with IDSS 
8 mA and VP  4 V.
486 FET AMPLIFIERS Effect of ID on gm
A mathematical relationship between gm and the dc bias current ID can be derived by not-
ing that Shockley’s equation can be written in the following form:

VGS ID
1 - = (8.8)
VP A IDSS

Substituting Eq. (8.8) into Eq. (8.6) results in

VGS ID
gm = gm0 a 1 - b = gm0 (8.9)
VP A IDSS

Using Eq. (8.9) to determine gm for a few specific values of ID, we obtain the following
results:
a. If ID = IDSS,
IDSS
gm = gm0 = gm0
A IDSS
b. If ID = IDSS >2,
IDSS >2
gm = gm0 = 0.707gm0
A IDSS
c. If ID = IDSS >4,
IDSS >4 gm0
gm = gm0 = = 0.5gm0
A IDSS 2

EXAMPLE 8.4 Plot gm versus ID for the JFET of Examples 8.1 through 8.3.
Solution: See Fig. 8.5.

gm (S)

4 mS
4

3 2.83 mS

2 mS
2

0 1 2 3 4 5 6 7 8 9 10 ID (mA)
IDSS IDSS IDSS
4 2

FIG. 8.5
Plot of gm versus ID for a JFET with IDSS  8 mA and VGS  4 V.

The plots of Examples 8.3 and 8.4 clearly reveal that

the highest values of gm are obtained when VGS approaches 0 V and ID approaches its
maximum value of IDSS.
JFET Input Impedance Zi JFET SMALL-SIGNAL 487
MODEL
The input impedance of all commercially available JFETs is sufficiently large to assume
that the input terminals approximate an open circuit. In equation form,

Zi (JFET) =   (8.10)

For a JFET a practical value of 109  (1000 M) is typical, whereas a value of 1012 
to 1015  is typical for MOSFETs and MESFETs.

JFET Output Impedance Zo

The output impedance of JFETs is similar in magnitude to that of conventional BJTs. On
JFET specification sheets, the output impedance will typically appear as gos or yos with the
units of mS. The parameter yos is a component of an admittance equivalent circuit, with the
subscript o signifying an output network parameter and s the terminal (source) to which it
is attached in the model. For the JFET of Fig. 6.20, gos has a range of 10 mS to 50 mS or
20 k (R = 1>G = 1>50 mS) to 100 k (R = 1>G = 1>10 mS).
In equation form,

1 1
Zo (JFET) = rd = = (8.11)
gos yos

The output impedance is defined on the characteristics of Fig. 8.6 as the slope of the
horizontal characteristic curve at the point of operation. The more horizontal the curve, the
greater is the output impedance. If it is perfectly horizontal, the ideal situation is on hand
with the output impedance being infinite (an open circuit)—an often applied approximation.
In equation form,

VDS
rd = ` (8.12)
ID VGS = constant

Note the requirement when applying Eq. (8.12) that the voltage VGS remain constant
when rd is determined. This is accomplished by drawing a straight line approximating the
VGS line at the point of operation. A  VDS or  ID is then chosen and the other quantity
measured off for use in the equation.

ID (mA)

VGS = 0 V

ΔVDS
rd = VGS = constant at −1 V
ΔID
VGS
Q-point
−1 V
Δ ID
ΔVDS

−2 V

0 VDS (V)

FIG. 8.6
Definition of rd using JFET drain characteristics.

EXAMPLE 8.5 Determine the output impedance for the JFET of Fig. 8.7 for VGS = 0 V
and VGS = -2 V at VDS = 8 V.
488 FET AMPLIFIERS ID (mA)

8 VGS = 0 V
7 Δ ID = 0.2 mA
ΔVDS = 5 V
6
VGS = −1 V
5
4
3 VGS = −2 V
Δ ID = 0.1 mA
2 Δ VDS = 8 V

1 VGS = −3 V
VGS = −4 V
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VDS (V)
FIG. 8.7
Drain characteristics used to calculate rd in Example 8.5.

Solution: For VGS = 0 V, a tangent line is drawn and  VDS is chosen as 5 V, resulting in
a  ID of 0.2 mA. Substituting into Eq. (8.12), we find
VDS 5V
rd = ` = = 25 k⍀
ID VGS = 0 V 0.2 mA
For VGS = -2 V, a tangent line is drawn and  VDS is chosen as 8 V, resulting in a  ID of
0.1 mA. Substituting into Eq. (8.12), we find
VDS 8V
rd = ` = = 80 k
ID VGS = -2 V 0.1 mA
which shows that rd does change from one operating region to another, with lower values
typically occurring at lower levels of VGS (closer to 0 V).

JFET AC Equivalent Circuit

Now that the important parameters of an ac equivalent circuit have been introduced and
discussed, a model for the JFET transistor in the ac domain can be constructed. The control
of Id by Vgs is included as a current source gmVgs connected from drain to source as shown
in Fig. 8.8. The current source has its arrow pointing from drain to source to establish a
180° phase shift between output and input voltages as will occur in actual operation.

G D
+

Vgs gmVgs rd

−
S S

FIG. 8.8
JFET ac equivalent circuit.

The input impedance is represented by the open circuit at the input terminals and the out-
put impedance by the resistor rd from drain to source. Note that the gate-to-source voltage is
now represented by Vgs (lowercase subscripts) to distinguish it from dc levels. In addition,
note that the source is common to both input and output circuits, whereas the gate and drain
terminals are only in “touch” through the controlled current source gmVgs.
In situations where rd is ignored (assumed sufficiently large in relation to other elements
of the network to be approximated by an open circuit), the equivalent circuit is simply a
current source whose magnitude is controlled by the signal Vgs and parameter gm—clearly
a voltage-controlled current source.
 FIXED-BIAS 489
EXAMPLE 8.6 Given gfs = 3.8 mS and gos = 20 mS, sketch the FET ac equivalent model. CONFIGURATION

Solution:
1 1
gm = gfs = 3.8 mS and rd = = = 50 k
gos 20 mS
resulting in the ac equivalent model of Fig. 8.9.

G D
+

rd
Vgs 3.8 × 10−3 Vgs
50 kΩ

−
S S

FIG. 8.9
JFET ac equivalent model for Example 8.6.

8.3 FIXED-BIAS CONFIGURATION

●
Now that the JFET equivalent circuit has been defined, a number of fundamental JFET
small-signal configurations are investigated. The approach parallels the ac analysis of BJT
amplifiers with a determination of the important parameters of Zi, Zo, and Av for each
configuration.
The fixed-bias configuration of Fig. 8.10 includes the coupling capacitors C1 and C2,
which isolate the dc biasing arrangement from the applied signal and load; they act as short-
circuit equivalents for the ac analysis.

+VDD

RD
C2
D
Vo
C1
G
Vi

RG S
Zo
Zi –
VGG
+

FIG. 8.10
JFET fixed-bias configuration.

Once the levels of gm and rd are determined from the dc biasing arrangement, specifica-
tion sheet, or characteristics, the ac equivalent model can be substituted between the ap-
propriate terminals as shown in Fig. 8.11. Note that both capacitors have the short-circuit
equivalent because the reactance XC = 1>(2pfC) is sufficiently small compared to other
impedance levels of the network, and the dc batteries VGG and VDD are set to 0 V by a
short-circuit equivalent.
The network of Fig. 8.11 is then carefully redrawn as shown in Fig. 8.12. Note the de-
fined polarity of Vgs, which defines the direction of gmVgs. If Vgs is negative, the direction
of the current source reverses. The applied signal is represented by Vi and the output signal
across RD 储 rd by Vo.
490 FET AMPLIFIERS XC ≈ 0 Ω XC ≈ 0 Ω
1 2
G D
Vi Vo

RG gmVgs RD
rd
Zi
Zo

Battery VGG Battery VDD

replaced by replaced by
short S short

FIG. 8.11
Substituting the JFET ac equivalent circuit unit into the network of
Fig. 8.10.

G D
+ + +
Zi Zo
Vi RG Vgs gmVgs rd RD Vo

– – –

FIG. 8.12
Redrawn network of Fig. 8.11.

Zi Figure 8.12 clearly reveals that

Zi = RG (8.13)

because of the infinite input impedance at the input terminals of the JFET.

Zo Setting Vi = 0 V as required by the definition of Zo will establish Vgs as 0 V also. The

result is gmVgs = 0 mA, and the current source can be replaced by an open-circuit equiva-
lent as shown in Fig. 8.13. The output impedance is

Zo = RD 储 rd (8.14)

gmVgs = 0 mA rd RD Zo

S
FIG. 8.13
Determining Zo.

If the resistance rd is sufficiently large (at least 10:1) compared to RD, the approximation
rd 储 RD ⬵ RD can often be applied and

Zo ⬵ RD rd Ú 10RD
(8.15)

Av Solving for Vo in Fig. 8.12, we find

Vo = -gmVgs (rd 储 RD)
but Vgs = Vi
and Vo = -gmVi (rd 储 RD)
so that FIXED-BIAS 491
CONFIGURATION
Vo
Av = = -gm (rd 储 RD) (8.16)
Vi
If rd Ú 10RD,

Vo
Av = = -gmRD (8.17)
Vi rd Ú 10RD

Phase Relationship The negative sign in the resulting equation for Av clearly reveals a
phase shift of 180° between input and output voltages.

EXAMPLE 8.7 The fixed-bias configuration of Example 7.1 had an operating point defined
by VGSQ = -2 V and IDQ = 5.625 mA, with IDSS = 10 mA and VP = -8 V. The network
is redrawn as Fig. 8.14 with an applied signal Vi. The value of yos is provided as 40 mS.
a. Determine gm.
b. Find rd.
c. Determine Zi.
d. Calculate Zo.
e. Determine the voltage gain Av.
f. Determine Av ignoring the effects of rd.

20 V

RD 2 kΩ
C2
D
C1 +
G IDSS = 10 mA
+ VP = −8 V
RG 1 MΩ S Vo
Vi Zo
Zi –
2V
– + –

FIG. 8.14
JFET configuration for Example 8.7.

Solution:
2IDSS 2(10 mA)
a. gm0 = = = 2.5 mS
0 VP 0 8V
VGSQ (-2 V)
gm = gm0 a 1 - b = 2.5 mS a 1 - b = 1.88 mS
VP (-8 V)
1 1
b. rd = = = 25 k⍀
yos 40 mS
c. Zi = RG = 1 M⍀
d. Zo = RD 储 rd = 2 k 储 25 k = 1.85 k⍀
e. Av = -gm(RD 储 rd) = -(1.88 mS)(1.85 k)
= ⴚ3.48
f. Av = -gmRD = -(1.88 mS)(2 k) = ⴚ3.76
As demonstrated in part (f), a ratio of 25 k:2 k = 12.5:1 between rd and RD results
in a difference of 8% in the solution.
492 FET AMPLIFIERS 8.4 SELF-BIAS CONFIGURATION
●
Bypassed RS
The fixed-bias configuration has the distinct disadvantage of requiring two dc voltage
sources. The self-bias configuration of Fig. 8.15 requires only one dc supply to establish
the desired operating point.

VDD

RD
C2
D
Vo
C1
G
Vi
S
Zo
RG
Zi
RS CS

FIG. 8.15
Self-bias JFET configuration.

The capacitor CS across the source resistance assumes its open-circuit equivalence for
dc, allowing RS to define the operating point. Under ac conditions, the capacitor assumes
the short-circuit state and “short circuits” the effects of RS. If left in the ac, gain will be
reduced, as will be shown in the paragraphs to follow.
The JFET equivalent circuit is established in Fig. 8.16 and carefully redrawn in Fig. 8.17.
Since the resulting configuration is the same as appearing in Fig. 8.12, the resulting
equations for Zi, Zo, and Av will be the same.

XC ≈ 0 Ω XC ≈ 0 Ω
1 2
G D
Vi Vo

gmVgs rd

Zo
Zi RG RD

S
RS bypassed VDD
by X C
S

FIG. 8.16
Network of Fig. 8.15 following the substitution of
the JFET ac equivalent circuit.

G D
+ + +
Zi Zo
Vi RG Vgs gmVgs rd RD Vo

– – S –

FIG. 8.17
Redrawn network of Fig. 8.16.
 SELF-BIAS 493
Zi Zi = RG (8.18) CONFIGURATION

Zo Zo = rd 储 RD (8.19)

If rd Ú 10RD,

Zo ⬵ RD (8.20)
rd Ú 10RD

Av

Av = -gm(rd 储 RD) (8.21)

If rd Ú 10RD,

Av = -gmRD (8.22)
rd Ú 10RD

Phase Relationship The negative sign in the solutions for Av again indicates a phase shift
of 180° between Vi and Vo.

Unbypassed RS
If CS is removed from Fig 8.15, the resistor RS will be part of the ac equivalent circuit as
shown in Fig. 8.18. In this case, there is no obvious way to reduce the network to lower its
level of complexity. In determining the levels of Zi, Zo, and Av, one must be very careful
with notation and defined polarities and direction. Initially, the resistance rd will be left out
of the analysis to form a basis for comparison.

G D
+ + +
ID Io
gmVgs
Zi Vgs Zo
S
Vi RG – RD Vo

RS
Io
– –

FIG. 8.18
Self-bias JFET configuration including the effects of RS with
rd  .

Zi Due to the open-circuit condition between the gate and the output network, the input
remains the following:

Zi = RG (8.23)

Zo The output impedance is defined by

Vo
Zo = `
Io Vi = 0
Setting Vi = 0 V in Fig. 8.18 results in the gate terminal being at ground potential (0 V).
The voltage across RG is then 0 V, and RG has been effectively “shorted out” of the picture.
Applying Kirchhoff’s current law results in
Io + ID = gmVgs
with Vgs = -(Io + ID)RS
494 FET AMPLIFIERS so that Io + ID = -gm (Io + ID)RS = -gm Io RS - gm ID RS
or Io[1 + gmRS] = -ID[1 + gmRS]
and Io = -ID (the controlled current source gmVgs = 0 A
for the applied conditions)
Since Vo = -IDRD
then Vo = -(-Io)RD = IoRD

Vo
and Zo = = RD (8.24)
Io
rd =  

If rd is included in the network, the equivalent will appear as shown in Fig. 8.19.

G a D

+ + + +
Io
I′ ID
gmVgs rd
Zi
− Zo
Vgs
Vi RG S RD Vo
−

RS

− −

Io + ID Io

FIG. 8.19
Including the effects of rd in the self-bias JFET configuration.

Vo IDRD
Since Zo = ` = -
Io Vi = 0 V Io
we should try to find an expression for Io in terms of ID.
Applying Kirchhoff’s current law, we have
Io = gmVgs + Ird - ID
but Vrd = Vo + Vgs
Vo + Vgs
and Io = gmVgs + - ID
rd
1 IDRD
or Io = a gm + b Vgs - - ID using Vo = -IDRD
rd rd
Now, Vgs = -(ID + Io)RS
1 IDRD
so that Io = - a gm + b (ID + Io)RS - - ID
rd rd
RS RS RD
with the result that Io c 1 + gmRS + d = -ID c 1 + gmRS + + d
rd rd rd
RS RD
-ID c 1 + gmRS + + d
rd rd
or Io =
RS
1 + gmRS +
rd
Vo -IDRD
and Zo = =
Io RS RD
-ID a 1 + gmRS + + b
rd rd
RS
1 + gmRS +
rd
 SELF-BIAS 495
RS CONFIGURATION
c 1 + gmRS +
d
rd
and finally, Zo = R (8.25a)
RS RD D
c 1 + gmRS + + d
rd rd

For rd Ú 10RD,
RS RD
a 1 + gmRS + b W
rd rd
RS RD RS
and 1 + gmRS + + ⬵ 1 + gmRS +
rd rd rd
resulting in

Zo ⬵ RD (8.25b)
rd Ú 10RD

Av For the network of Fig. 8.19, application of Kirchhoff’s voltage law to the input cir-
cuit results in
Vi - Vgs - VRS = 0
Vgs = Vi - IDRS
The voltage across rd using Kirchhoff’s voltage law is
Vrd = Vo - VRS
Vrd Vo - VRS
and I = =
rd rd
so that application of Kirchhoff’s current law results in
Vo - VRS
ID = gmVgs +
rd
Substituting for Vgs from above and substituting for Vo and VRS, we have
(-IDRD) - (IDRS)
ID = gm 3 Vi - IDRS 4 +
rd
RD + RS
so that ID c 1 + gmRS + d = gmVi
rd
gmVi
or ID =
RD + RS
1 + gmRS +
rd
The output voltage is then
gmRDVi
Vo = -IDRD = -
RD + RS
1 + gmRS +
rd

Vo gmRD
and Av = = - (8.26)
Vi RD + RS
1 + gmRS +
rd

Again, if rd Ú 10(RD + RS),

Vo gmRD
Av = ⬵ - (8.27)
Vi 1 + gmRS
rd Ú 10(RD + RS)

Phase Relationship The negative sign in Eq. (8.26) again reveals that a 180° phase shift
will exist between Vi and Vo.
496 FET AMPLIFIERS
EXAMPLE 8.8 The self-bias configuration of Example 7.2 has an operating point defined
by VGSQ = -2.6 V and IDQ = 2.6 mA, with IDSS = 8 mA and VP = -6 V. The network
is redrawn as Fig. 8.20 with an applied signal Vi. The value of gos is given as 20 mS.
a. Determine gm.
b. Find rd.
c. Find Zi.
d. Calculate Zo with and without the effects of rd. Compare the results.
e. Calculate Av with and without the effects of rd. Compare the results.

20 V

RD 3.3 kΩ
C2
D Vo
C1
Vi
G IDSS = 8 mA
VP = −6 V

S
Zi Zo
RG 1 MΩ RS 1 kΩ

FIG. 8.20
Network for Example 8.8.

Solution:
2IDSS 2(8 mA)
a. gm0 = = = 2.67 mS
0 VP 0 6V
VGSQ (-2.6 V)
gm = gm0 a 1 - b = 2.67 mS a 1 - b = 1.51 mS
VP (-6 V)
1 1
b. rd = = = 50 k⍀
yos 20 mS
c. Zi = RG = 1 M
d. With rd,
rd = 50 k 7 10RD = 33 k
Therefore,
Zo = RD = 3.3 k⍀
If rd =  ,
Zo = RD = 3.3 k⍀
e. With rd,
-gmRD -(1.51 mS)(3.3 k)
Av = =
RD + RS 3.3 k + 1 k
1 + gmRS + 1 + (1.51 mS)(1 k) +
rd 50 k
= ⴚ1.92
With rd    (open-circuit equivalence),
-gmRD -(1.51 mS)(3.3 k)
Av = = = ⴚ1.98
1 + gmRS 1 + (1.51 mS)(1 k)
As above, the effect of rd is minimal because the condition rd Ú 10(RD + RS) is satisfied.
Note also that the typical gain of a JFET amplifier is less than that generally encountered
for BJTs of similar configurations. Keep in mind, however, that Zi is magnitudes greater than
the typical Zi of a BJT, which will have a very positive effect on the overall gain of a system.
8.5 VOLTAGE-DIVIDER CONFIGURATION VOLTAGE-DIVIDER 497
● CONFIGURATION
The popular voltage-divider configuration for BJTs can also be applied to JFETs as dem-
onstrated in Fig. 8.21.

+VDD

RD
R1 C2
Vo
C1 D
G

Zo
S
+
Vi R2
Zi RS CS
–

FIG. 8.21
JFET voltage-divider configuration.

Substituting the ac equivalent model for the JFET results in the configuration of Fig. 8.22.
Replacing the dc supply VDD by a short-circuit equivalent has grounded one end of R1 and
RD. Since each network has a common ground, R1 can be brought down in parallel with
R2 as shown in Fig. 8.23. RD can also be brought down to ground, but in the output circuit
across rd. The resulting ac equivalent network now has the basic format of some of the
networks already analyzed.

Zi R1 and R2 are in parallel with the open-circuit equivalence of the JFET, resulting in

Zi = R1 储 R2 (8.28)

Zo Setting Vi = 0 V sets Vgs and gmVgs to zero, and

Zo = rd 储 RD (8.29)

For rd Ú 10RD,

Zo ⬵ RD (8.30)
rd Ú 10RD

R1 RD

G D G D
Vi Vo Vi Vo
+ +
Zi Zo
R2 gmVgs RD
Zi Vgs Zo R1 R2 Vgs gmVgs rd RD

– S –

FIG. 8.22 FIG. 8.23

Network of Fig. 8.21 under ac conditions. Redrawn network of Fig. 8.22.
498 FET AMPLIFIERS Av
Vgs = Vi
and Vo = -gmVgs(rd 储 RD)
Vo -gmVgs(rd 储 RD)
so that Av = =
Vi Vgs

Vo
and Av = = -gm(rd 储 RD) (8.31)
Vi

Vo
If rd Ú 10RD, Av = ⬵ -gmRD (8.32)
Vi rd Ú 10RD

Note that the equations for Zo and Av are the same as obtained for the fixed-bias and self-
bias (with bypassed RS) configurations. The only difference is the equation for Zi, which is
now sensitive to the parallel combination of R1 and R2.

8.6 COMMON-GATE CONFIGURATION

●
The last JFET configuration to be analyzed in detail is the common-gate configuration of
Fig. 8.24, which parallels the common-base configuration employed with BJT transistors.
Substituting the JFET equivalent circuit results in Fig. 8.25. Note the continuing re-
quirement that the controlled source gmVgs be connected from drain to source with rd in
parallel. The isolation between input and output circuits has obviously been lost since the
gate terminal is now connected to the common ground of the network and the controlled
current source is connected directly from drain to source. In addition, the resistor con-
nected between input terminals is no longer RG, but the resistor RS connected from source
to ground. Note also the location of the controlling voltage Vgs and the fact that it appears
directly across the resistor RS.

rd
– +
C1 C2
C1 a S D b
C2
S D + – +
+ + gmVgs Z'o
Zi Zo
Vi RS Vgs RD Vo
Zi RD Zo
Vi G Z'i
RS Vo
Z'i + – –
VDD +G
– – –

FIG. 8.24 FIG. 8.25

JFET common-gate configuration. Network of Fig. 8.24 following substitution of JFET ac
equivalent model.

Zi The resistor RS is directly across the terminals defining Zi. Let us therefore find the
impedance Zi of Fig. 8.24, which will simply be in parallel with RS when Zi is defined.
The network of interest is redrawn as Fig. 8.26. The voltage V = -Vgs. Applying
Kirchhoff’s voltage law around the output perimeter of the network results in
V - Vrd - VRD = 0
and Vrd = V - VRD = V - IRD
Applying Kirchhoff’s current law at node a results in
I + gmVgs = Ird
(V - IRD)
and I = Ird - gmVgs = - gmVgs
rd
V IRD
or I = - - gm [-V]
rd rd
 I' I' COMMON-GATE 499
CONFIGURATION
+ – a

Ird +
Z'i
gmVgs rd V rd
V' Vgs
–
+
RD VRD
– + I'
–

FIG. 8.26
Determining Zi for the network of Fig. 8.24.

RD 1
so that Ic 1 + d = Vc + gm d
rd rd

RD
c1 + d
V rd
and Zi = = (8.33)
I 1
c gm + d
rd

V rd + RD
or Zi = =
I 1 + gmrd
and Zi = RS 储 Zi

rd + RD
which results in Zi = RS 储 c d (8.34)
1 + gmrd

If rd Ú 10RD, Eq. (8.33) permits the following approximation since RD>rd V 1 and
1>rd V gm:
RD
c1 + d
rd 1
Zi = ⬵
1 gm
c gm + d
rd

and Zi ⬵ RS 储 1>gm rd Ú 10RD

(8.35)

Zo Substituting Vi = 0 V in Fig. 8.25 will “short-out” the effects of RS and set Vgs to 0 V.
The result is gmVgs = 0, and rd will be in parallel with RD. Therefore,

Zo = RD 储 rd (8.36)

For rd Ú 10RD,

Zo ⬵ RD (8.37)
rd Ú 10RD

Av Figure 8.25 reveals that

Vi = -Vgs
and Vo = IDRD
The voltage across rd is
Vrd = Vo - Vi
500 FET AMPLIFIERS Vo - Vi
and Ird =
rd
Applying Kirchhoff’s current law at node b in Fig. 8.25 results in
Ird + ID + gmVgs = 0
and ID = -Ird - gmVgs
Vo - Vi
= -c d - gm 3 -Vi 4
rd
Vi - Vo
ID = + gmVi
rd
Vi - Vo
so that Vo = ID RD = c + gmVi d RD
rd
Vi RD Vo RD
= - + gm
rd rd
RD RD
and Vo c 1 + d = Vi c + gmRD d
rd rd

RD
c gmRD + d
Vo rd
with Av = = (8.38)
Vi RD
c1 + d
rd

For rd Ú 10RD, the factor RD>rd of Eq. (8.38) can be dropped as a good approximation, and

Av ⬵ gmRD (8.39)
rd Ú 10RD

Phase Relationship The fact that Av is a positive number will result in an in-phase rela-
tionship between Vo and Vi for the common-gate configuration.

EXAMPLE 8.9 Although the network of Fig. 8.27 may not initially appear to be of the
common-gate variety, a close examination will reveal that it has all the characteristics of
Fig. 8.24. If VGSQ = -2.2 V and IDQ = 2.03 mA:
a. Determine gm.
b. Find rd.
c. Calculate Zi with and without rd. Compare results.
d. Find Zo with and without rd. Compare results.
e. Determine Vo with and without rd. Compare results.
+12 V

RD 3.6 kΩ

10 μ F
D Vo

IDSS = 10 mA
G
VP = − 4 V
gos = 50 μS

S
+ 10 μ F
Vi = 40 mV RS 1.1 kΩ
–

FIG. 8.27
Network for Example 8.9.
Solution: SOURCE-FOLLOWER 501
(COMMON-DRAIN)
2IDSS 2(10 mA) CONFIGURATION
a. gm0 = = = 5 mS
0 VP 0 4V
VGSQ (-2.2 V)
gm = gm0 a 1 - b = 5 mS a 1 - b = 2.25 mS
VP (-4 V)
1 1
b. rd = = = 20 k⍀
gos 50 mS
c. With rd,
rd + RD 20 k + 3.6 k
Zi = RS 储 c d = 1.1 k 储 c d
1 + gmrd 1 + (2.25 mS)(20 k)
= 1.1 k 储 0.51 k = 0.35 k⍀
Without rd,
Zi = RS 储 1>gm = 1.1 k 储 1>2.25 ms = 1.1 k 储 0.44 k
= 0.31 k⍀
Even though the condition rd Ú 10RD is not satisfied with rd = 20 k and
10RD = 36 k, both equations result in essentially the same level of impedance. In
this case, 1>gm was the predominant factor.
d. With rd,
Zo = RD 储 rd = 3.6 k 储 20 k = 3.05 k⍀
Without rd,
Zo = RD = 3.6 k⍀
Again the condition rd Ú 10RD is not satisfied, but both results are reasonably close.
RD is certainly the predominant factor in this example.
e. With rd,
RD 3.6 k
c gmRD + d c (2.25 mS)(3.6 k) + d
rd 20 k
Av = =
RD 3.6 k
c1 + d c1 + d
rd 20 k
8.1 + 0.18
= = 7.02
1 + 0.18
Vo
and Av = 1 Vo = AvVi = (7.02)(40 mV) = 280.8 mV
Vi
Without rd,
Av = gmRD = (2.25 mS)(3.6 k) = 8.1
with Vo = AvVi = (8.1)(40 mV) = 324 mV
In this case, the difference is a little more noticeable, but not dramatically so.

Example 8.9 demonstrates that even though the condition rd Ú 10RD was not satisfied,
the results for the parameters given were not significantly different using the exact and ap-
proximate equations. In fact, in most cases, the approximate equations can be used to find
a reasonable idea of particular levels with a reduced amount of effort.

8.7 SOURCE-FOLLOWER (COMMON-DRAIN)

CONFIGURATION
●
The JFET equivalent of the BJT emitter-follower configuration is the source-follower con-
figuration of Fig. 8.28. Note that the output is taken off the source terminal and, when the
dc supply is replaced by its short-circuit equivalent, the drain is grounded (hence, the ter-
minology common-drain).
Substituting the JFET equivalent circuit results in the configuration of Fig. 8.29. The
controlled source and the internal output impedance of the JFET are tied to ground at
one end and RS on the other, with Vo across RS. Since gmVgs, rd, and RS are connected to
502 FET AMPLIFIERS VDD

D
C1
G
Vi

C2
S
Vo
Zi
RG
RS Zo

FIG. 8.28
JFET source-follower configuration.

G D
Vi
+

Vgs gmVgs rd
Zi

–
RG
S Vo

RS Zo

FIG. 8.29
Network of Fig. 8.28 following the substitution of the JFET ac
equivalent model.

the same terminal and ground, they can all be placed in parallel as shown in Fig. 8.30.
The current source reversed direction, but Vgs is still defined between the gate and source
terminals.

S Io
G
Vi
+ Vgs – +
Zi Zo
RG gmVgs rd RS Vo

D
–

FIG. 8.30
Network of Fig. 8.29 redrawn.

Zi Figure 8.30 clearly reveals that Zi is defined by

Zi = RG (8.40)

Zo Setting Vi = 0 V results in the gate terminal being connected directly to the ground as
shown in Fig. 8.31.
The fact that Vgs and Vo are across the same parallel network results in Vo = -Vgs.
 S
Io SOURCE-FOLLOWER 503
(COMMON-DRAIN)
– + CONFIGURATION
Zo
Vgs gmVgs rd Vo
RS

+ –

FIG. 8.31
Determining Zo for the network of Fig. 8.30.

Applying Kirchhoff’s current law at node S, we obtain

Io + gmVgs = Ird + IRs
Vo Vo
= +
rd RS
1 1
The result is Io = Vo c + d - gmVgs
rd RS
1 1
= Vo c + d - gm[-Vo]
rd RS
1 1
= Vo c + + gm d
rd RS
Vo Vo 1 1
and Zo = = = =
Io 1 1 1 1 1 1 1
Vo c + + gm d + + gm + +
rd RS rd RS rd RS 1>gm
which has the same format as the total resistance of three parallel resistors. Therefore,

Zo = rd 储 RS 储 1>gm (8.41)

For rd Ú 10 RS,

Zo ⬵ RS 储 1>gm (8.42)
rd Ú 10RS

Av The output voltage Vo is determined by

Vo = gmVgs(rd 储 RS)
and applying Kirchhoff’s voltage law around the perimeter of the network of Fig. 8.30
results in
Vi = Vgs + Vo
and Vgs = Vi - Vo
so that Vo = gm(Vi - Vo)(rd 储 RS)
or Vo = gmVi(rd 储 RS) - gmVo(rd 储 RS)
and Vo[1 + gm(rd 储 RS)] = gmVi(rd 储 RS)

Vo gm(rd 储 RS)
so that Av = = (8.43)
Vi 1 + gm(rd 储 RS)

In the absence of rd or if rd Ú 10 RS,

Vo gmRS
Av = ⬵ (8.44)
Vi 1 + gmRS rd Ú 10RS

Since the denominator of Eq. (8.43) is larger than the numerator by a factor of one, the
gain can never be equal to or greater than one (as encountered for the emitter-follower BJT
network).
504 FET AMPLIFIERS Phase Relationship Since Av of Eq. (8.43) is a positive quantity, Vo and Vi are in phase
for the JFET source-follower configuration.

EXAMPLE 8.10 A dc analysis of the source-follower network of Fig. 8.32 results in

VGSQ = -2.86 V and IDQ = 4.56 mA.
a. Determine gm.
b. Find rd.
c. Determine Zi.
d. Calculate Zo with and without rd. Compare results.
e. Determine Av with and without rd. Compare results.

+9 V

IDSS = 16 mA
VP = − 4 V
gos = 25 μS

+ 0.05 μ F

Vi RG 1 MΩ 0.05 μ F
+
Zi
RS 2.2 kΩ Vo
– Zo
–

FIG. 8.32
Network to be analyzed in Example 8.10.

Solution:
2IDSS 2(16 mA)
a. gm0 = = = 8 mS
0 VP 0 4V
VGSQ (-2.86 V)
gm = gm0 a 1 - b = 8 mS a 1 - b = 2.28 mS
VP (-4 V)
1 1
b. rd = = = 40 k⍀
gos 25 mS
c. Zi = RG = 1 M⍀
d. With rd,
Zo = rd 储 RS 储 1>gm = 40 k 储 2.2 k 储 1>2.28 mS
= 40 k 储 2.2 k 储 438.6 
= 362.52 ⍀
which shows that Zo is often relatively small and determined primarily by 1>gm.
Without rd,
Zo = RS 储 1>gm = 2.2 k 储 438.6  = 365.69 ⍀
which shows that rd typically has little effect on Zo.
e. With rd,
gm(rd 储 RS) (2.28 mS)(40 k 储 2.2 k)
Av = =
1 + gm(rd 储 RS) 1 + (2.28 mS)(40 k 储 2.2 k)
(2.28 mS)(2.09 k) 4.77
= = = 0.83
1 + (2.28 mS)(2.09 k) 1 + 4.77
which is less than 1, as predicted above.
 Without rd, DEPLETION-TYPE 505
gm RS MOSFETs
(2.28 mS)(2.2 k)
Av = =
1 + gm RS 1 + (2.28 mS)(2.2 k)
5.02
= = 0.83
1 + 5.02
which shows that rd usually has little effect on the gain of the configuration.

8.8 DEPLETION-TYPE MOSFETs

●
The fact that Shockley’s equation is also applicable to depletion-type MOSFETs
(D-MOSFETs) results in the same equation for gm. In fact, the ac equivalent model for
D-MOSFETs shown in Fig. 8.33 is exactly the same as that employed for JFETs, as shown
in Fig. 8.8.
The only difference offered by D-MOSFETs is that VGSQ can be positive for n-channel de-
vices and negative for p-channel units. The result is that gm can be greater than gm0, as demon-
strated by the example to follow. The range of rd is very similar to that encountered for JFETs.

G G D
D +

G Vgs gmVgs rd

S
S
– S

FIG. 8.33
D-MOSFET ac equivalent model.

EXAMPLE 8.11 The network of Fig. 8.34 was analyzed as Example 7.7, resulting in
VGSQ = 0.35 V and IDQ = 7.6 mA.
a. Determine gm and compare to gm0.
b. Find rd.
c. Sketch the ac equivalent network for Fig. 8.34.
d. Find Zi.
e. Calculate Zo.
f. Find Av.

18 V

RD 1.8 kΩ
C2
R1 110 MΩ
D Vo

IDSS = 6 mA
C1 VP = − 3 V
G
Vi gos = 10 μS

Zi S
Zo
R2 10 MΩ RS 150 Ω CS

FIG. 8.34
Network for Example 8.11.
506 FET AMPLIFIERS Solution:
2IDSS 2(6 mA)
a. gm0 = = = 4 mS
0 VP 0 3V
VGSQ (+0.35 V)
gm = gm0 a 1 - b = 4 mS a 1 - b = 4 mS(1 + 0.117) = 4.47 mS
VP (-3 V)
1 1
b. rd = = = 100 k⍀
yos 10 mS
c. See Fig. 8.35. Note the similarities with the network of Fig. 8.23. Equations (8.28)
through (8.32) are therefore applicable.

G D
+ + +
Zi rd RD Zo
Vi R1 110 MΩ R2 10 MΩ Vgs 4.47 × 10 −3 Vgs 100 kΩ 1.8 kΩ Vo

– – –
S S

FIG. 8.35
AC equivalent circuit for Fig. 8.34.

d. Eq. (8.28): Zi = R1 储 R2 = 10 M 储 110 M = 9.17 M⍀

e. Eq. (8.29): Zo = rd 储 RD = 100 k 储 1.8 k = 1.77 k⍀ ⬵ RD = 1.8 k⍀
f. rd Ú 10RD S 100 k Ú 18 k
Eq. (8.32): Av = -gmRD = -(4.47 mS)(1.8 k) = 8.05

8.9 ENHANCEMENT-TYPE MOSFETs

●
The enhancement-type MOSFET (E-MOSFET) can be either an n-channel (nMOS) or
p-channel (pMOS) device, as shown in Fig. 8.36. The ac small-signal equivalent circuit of
either device is shown in Fig. 8.36, revealing an open-circuit between gate and drain–source
channel and a current source from drain to source having a magnitude dependent on the gate-
to-source voltage. There is an output impedance from drain to source rd, which is usually
provided on specification sheets as a conductance gos or admittance yos. The device transcon-
ductance gm is provided on specification sheets as the forward transfer admittance yfs.
In our analysis of JFETs, an equation for gm was derived from Shockley’s equation. For
E-MOSFETs, the relationship between output current and controlling voltage is defined by
ID = k(VGS - VGS(Th))2

G pMOS
G D
S
+
gmVgs rd
Vgs
D –
S
G nMOS
1 1
gm = gfs = yfs rd = g = y
os os
S

FIG. 8.36
Enhancement MOSFET ac small-signal model.
Since gm is still defined by E-MOSFET DRAIN- 507
FEEDBACK
ID CONFIGURATION
gm =
VGS
we can take the derivative of the transfer equation to determine gm as an operating point.
That is,
dID d d
gm = = k(VGS - VGS(Th))2 = k (V - VGS(Th))2
dVGS dVGS dVGS GS
d
= 2k(VGS - VGS(Th)) (V - VGS(Th)) = 2k(VGS - VGS(Th))(1 - 0)
dVGS GS

and gm = 2k(VGSQ - VGS(Th)) (8.45)

Recall that the constant k can be determined from a given typical operating point on a
specification sheet. In every other respect, the ac analysis is the same as that employed for
JFETs or D-MOSFETs. Be aware, however, that the characteristics of an E-MOSFET are
such that the biasing arrangements are somewhat limited.

8.10 E-MOSFET DRAIN-FEEDBACK CONFIGURATION

●
The E-MOSFET drain-feedback configuration appears in Fig. 8.37. Recall from dc calcula-
tions that RG could be replaced by a short-circuit equivalent since IG = 0 A and therefore
VRG = 0 V. However, for ac situations it provides an important high impedance between Vo
and Vi. Otherwise, the input and output terminals would be connected directly and Vo = Vi.

VDD

RD RF
RF C2
Vo Ii Ii
D G D
Vo
Zo Zi
+ Zo
C1 + gmVgs rd RD
Vi Vi Vgs
G
S – –
Zi S

FIG. 8.37 FIG. 8.38

E-MOSFET drain-feedback configuration. AC equivalent of the network of Fig. 8.37.

Substituting the ac equivalent model for the device results in the network of Fig. 8.38.
Note that RF is not within the shaded area defining the equivalent model of the device, but
does provide a direct connection between input and output circuits.

Zi Applying Kirchhoff’s current law to the output circuit (at node D in Fig. 8.38) results in
Vo
Ii = gmVgs +
rd 储 RD
and Vgs = Vi
Vo
so that Ii = gmVi +
rd 储 RD
Vo
or Ii - gmVi =
rd 储 RD
Therefore, Vo = (rd 储 RD)(Ii - gmVi)
Vi - Vo Vi - (rd 储 RD)(Ii - gmVi)
with Ii = =
RF RF
508 FET AMPLIFIERS and IiRF = Vi - (rd 储 RD)Ii + (rd 储 RD)gmVi
so that Vi [1 + gm(rd 储 RD)] = Ii [RF + rd 储 RD]

Vi RF + rd 储 RD
and finally, Zi = = (8.46)
Ii 1 + gm(rd 储 RD)

Typically, RF W rd 储 RD, so that

RF
Zi ⬵
1 + gm(rd 储 RD)
For rd Ú 10RD,

RF
Zi ⬵ (8.47)
1 + gmRD RF W rd 储 RD, rd Ú 10RD

Zo Substituting Vi = 0 V results in Vgs = 0 V and gmVgs = 0, with a short-circuit path

from gate to ground as shown in Fig. 8.39. RF, rd, and RD are then in parallel and

Zo = RF 储 rd 储 RD (8.48)

G RF D

Vi = Vgs = 0 V gmVgs = 0 mA rd RD
Zo

FIG. 8.39
Determining Zo for the network of Fig. 8.37.

Normally, RF is so much larger than rd 储 RD that

Zo ⬵ rd 储 RD
and with rd Ú 10RD,

Zo ⬵ RD (8.49)
RF W rd 储 RD, rd Ú 10RD

Av Applying Kirchhoff’s current law at node D of Fig. 8.38 results in

Vo
Ii = gmVgs +
rd 储 RD
Vi - Vo
but Vgs = Vi and Ii =
RF
Vi - Vo Vo
so that = gmVi +
RF rd 储 RD
Vi Vo Vo
and - = gmVi +
RF RF rd 储 RD
1 1 1
so that Vo c + d = Vi c - gm d
rd 储 RD RF RF
1
c - gm d
Vo RF
and Av = =
Vi 1 1
c + d
rd 储 RD RF
1 1 1
but + =
rd 储 RD RF RF 储 rd 储 RD
 1 E-MOSFET DRAIN- 509
and gm W FEEDBACK
RF
CONFIGURATION

so that Av = -gm(RF 储 rd 储 RD) (8.50)

Since RF is usually W rd 储 RD and if rd Ú 10RD,

Av ⬵ -gmRD (8.51)
RF W rd 储 RD, rd Ú 10RD

Phase Relationship The negative sign for Av reveals that Vo and Vi are out of phase
by 180°.

EXAMPLE 8.12 The E-MOSFET of Fig. 8.40 was analyzed in Example 7.10, with the
result that k = 0.24 * 10-3 A>V2, VGSQ = 6.4 V, and IDQ = 2.75 mA.
a. Determine gm.
b. Find rd.
c. Calculate Zi with and without rd. Compare results.
d. Find Zo with and without rd. Compare results.
e. Find Av with and without rd. Compare results.

12 V

RD 2 kΩ

Vo
1 μF
RF 10 MΩ Zo
ID ( on) = 6 mA
Vi VGS ( on) = 8 V
1 μF VGS ( Th) = 3 V
gos = 20 μS
Zi

FIG. 8.40
Drain-feedback amplifier from Example 8.11.

Solution:
a. gm = 2k(VGSQ - VGS(Th)) = 2(0.24 * 10-3 A>V2)(6.4 V - 3 V)
= 1.63 mS
1 1
b. rd = = = 50 k⍀
gos 20 mS
c. With rd,
RF + rd 储 RD 10 M + 50 k 储 2 k
Zi = =
1 + gm(rd 储 RD) 1 + (1.63 mS)(50 k 储 2 k)
10 M + 1.92 k
= = 2.42 M⍀
1 + 3.13
Without rd,
RF 10 M
Zi ⬵ = = 2.53 M⍀
1 + gmRD 1 + (1.63 mS)(2 k)
which shows that since the condition rd Ú 10RD = 50 k Ú 40 k is satisfied, the
results for Zo with or without rd will be quite close.
d. With rd,
Zo = RF 储 rd 储 RD = 10 M 储 50 k 储 2 k = 49.75 k 储 2 k
= 1.92 k⍀
510 FET AMPLIFIERS Without rd,
Zo ⬵ RD = 2 k⍀
again providing very close results.
e. With rd,
Av = -gm(RF 储 rd 储 RD)
= -(1.63 mS)(10 M 储 50 k 储 2 k)
= -(1.63 mS)(1.92 k)
= ⴚ3.21
Without rd,
Av = -gmRD = -(1.63 mS)(2 k)
= ⴚ3.26
which is very close to the above result.

8.11 E-MOSFET VOLTAGE-DIVIDER CONFIGURATION

●
The last E-MOSFET configuration to be examined in detail is the voltage-divider network
of Fig. 8.41. The format is exactly the same as appearing in a number of earlier discussions.
Substituting the ac equivalent network for the E-MOSFET results in the configuration
of Fig. 8.42, which is exactly the same as Fig. 8.23. The result is that Eqs. (8.28) through
(8.32) are applicable, as listed below for the E-MOSFET.

VDD

RD

R1 Vo
D
Zo
C1
G
Vi D
Vi G Vo
S
+
Zi Zi Zo
R2 Vgs
R1 R2 gmVgs rd RD
RS CS
–
S

FIG. 8.41 FIG. 8.42

E-MOSFET voltage-divider configuration. AC equivalent network for the configuration of Fig. 8.41.

Zi

Zi = R1 储 R2 (8.52)

Zo

Zo = rd 储 RD (8.53)

For rd Ú 10RD,

Zo ⬵ Rd rd Ú 10RD
(8.54)

Av

Vo
Av = = -gm(rd 储 RD) (8.55)
Vi
and if rd Ú 10RD, DESIGNING FET 511
AMPLIFIER NETWORKS
Vo
Av = ⬵ -gm RD (8.56)
Vi

8.12 DESIGNING FET AMPLIFIER NETWORKS

●
Design problems at this stage are limited to obtaining a desired dc bias condition or ac
voltage gain. In most cases, the various equations developed are used “in reverse” to define
the parameters necessary to obtain the desired gain, input impedance, or output imped-
ance. To avoid unnecessary complexity during the initial stages of the design, the approxi-
mate equations are often employed because some variation will occur when calculated
resistors are replaced by standard values. Once the initial design is completed, the results
can be tested and refinements made using the complete equations.
Throughout the design procedure be aware that although superposition permits a sepa-
rate analysis and design of the network from a dc and an ac viewpoint, a parameter chosen
in the dc environment will often play an important role in the ac response. In particular,
recall that the resistance RG could be replaced by a short-circuit equivalent in the feedback
configuration because IG ⬵ 0 A for dc conditions, but for the ac analysis, it presents an
important high-impedance path between Vo and Vi. In addition, recall that gm is larger for
operating points closer to the ID axis (VGS = 0 V), requiring that RS be relatively small.
In the unbypassed RS network, a small RS will also contribute to a higher gain, but for the
source-follower, the gain is reduced from its maximum value of 1. In total, simply keep
in mind that network parameters can affect the dc and ac levels in different ways. Often a
balance must be made between a particular operating point and its effect on the ac response.
In most situations, the available dc supply voltage is known, the FET to be employed has
been determined, and the capacitors to be employed at the chosen frequency are defined.
It is then necessary to determine the resistive elements necessary to establish the desired
gain or impedance level. The next three examples determine the required parameters for a
specific gain.

EXAMPLE 8.13 Design the fixed-bias network of Fig. 8.43 to have an ac gain of 10. That
is, determine the value of RD.

VDD (+30 V)

RD

D Vo
C1 IDSS = 10 mA
G
Vi VP = – 4 V
0.1 μF gos = 20 μ S
RG
10 MΩ S

FIG. 8.43
Circuit for desired voltage gain in Example 8.13.

Solution: Since VGSQ = 0 V, the level of gm is gm0. The gain is therefore determined by
Av = -gm(RD 储 rd) = -gm0(RD 储 rd)
2IDSS 2(10 mA)
with gm0 = = = 5 mS
0 VP 0 4V
The result is -10 = -5 mS(RD 储 rd)
10
and RD 储 rd = = 2 k
5 mS
512 FET AMPLIFIERS From the device specifications,
1 1
rd = = = 50 k
gos 20 * 10-6 S
Substituting, we find
RD 储 rd = RD 储 50 k = 2 k
RD(50 k)
and = 2 k
RD + 50 k
or 50RD = 2(RD + 50 k) = 2RD + 100 k
with 48RD = 100 k
100 k
and RD = ⬵ 2.08 k
48
The closest standard value is 2 k⍀ (Appendix D), which would be employed for this
design.
The resulting level of VDSQ is then determined as follows:
VDSQ = VDD - IDQ RD = 30 V - (10 mA)(2 k) = 10 V
The levels of Zi and Zo are set by the levels of RG and RD, respectively. That is,
Zi = RG = 10 M⍀
Zo = RD 储 rd = 2 k 储 50 k = 1.92 k⍀ ⬵ RD = 2 k

EXAMPLE 8.14 Choose the values of RD and RS for the network of Fig. 8.44 that will
result in a gain of 8 using a relatively high level of gm for this device defined at VGSQ = 14VP.

VDD
+20 V

RD
C2
Vo
C1 0.1 μF
0V
Vi RL
0.1 μF 10 MΩ

RG IDSS = 10 mA gm 0 = 5 mS
10 MΩ CS VP = – 4 V
RS 40 μF gos = 20 μ S

FIG. 8.44
Network for desired voltage gain in Example 8.14.

Solution: The operating point is defined by

1 1
VGSQ = VP = (-4 V) = -1 V
4 4
VGSQ 2 (-1 V) 2
and ID = IDSS a 1 - b = 10 mA a 1 - b = 5.625 mA
VP (-4 V)
Determining gm, we obtain
VGSQ
gm = gm0 a 1 - b
VP
(-1 V)
= 5 mS a 1 - b = 3.75 mS
(-4 V)
The magnitude of the ac voltage gain is determined by
0 Av 0 = gm(RD 储 rd)
Substituting known values results in SUMMARY TABLE 513
8 = (3.75 mS)(RD 储 rd)
8
so that RD 储 rd = = 2.13 k
3.75 mS
The level of rd is defined by
1 1
rd = = = 50 k
gos 20 mS
and RD 储 50 k = 2.13 k
with the result that
RD = 2.2 k⍀
which is a standard value.
The level of RS is determined by the dc operating conditions as follows:
VGSQ = -IDRS
-1 V = -(5.625 mA)RS
1V
and RS = = 177.8 
5.625 mA
The closest standard value is 180 ⍀. In this example, RS does not appear in the ac design
because of the shorting effect of CS.

In the next example, RS is unbypassed and the design becomes a bit more complicated.

EXAMPLE 8.15 Determine RD and RS for the network of Fig. 8.44 to establish a gain of 8
if the bypass capacitor CS is removed.
Solution: VGSQ and IDQ are still 1 V and 5.625 mA, respectively, and since the equation
VGS = -ID RS has not changed, RS continues to equal the standard value of 180 ⍀ obtained
in Example 8.14.
The gain of an unbypassed self-bias configuration is
gmRD
Av = -
1 + gmRS
For the moment it is assumed that rd Ú 10(RD + RS). Using the full equation for Av at
this stage of the design would simply complicate the process unnecessarily.
Substituting (for the specified magnitude of 8 for the gain), we obtain
-(3.75 mS)RD (3.75 mS)RD
080 = ` ` =
1 + (3.75 mS)(180 ) 1 + 0.675
and 8(1 + 0.675) = (3.75 mS)RD
13.4
so that RD = = 3.573 k
3.75 mS
with the closest standard value at 3.6 k⍀.
We can now test the condition
rd Ú 10(RD + RS)
We have 50 k Ú 10(3.6 k + 0.18 k) = 10(3.78 k)
and 50 k Ú 37.8 k
which is satisfied—the solution stands!

8.13 SUMMARY TABLE

●
To provide a quick comparison between configurations and offer a listing that can be help-
ful for a variety of reasons, Table 8.1 was developed. The exact and approximate equations
for each important parameter are provided with a typical range of values for each. Although
 TABLE 8.1
Zi, Zo, and Av for various FET configurations

Configuration Zi Zo Vo
Av =
Vi
Fixed-bias
[JFET or D-MOSFET]
Fixed-bias +VDD
[JFET or D-MOSFET] Medium (2 k) Medium (- 10)
RD
C2 High (10 M)
C1
Vo = RD 储 r d = - gm(rd 储 RD)
Vi = RG
Zo ⬵ RD ⬵ - gmRD (rd Ú 10 RD)
RG (rd Ú 10 RD)
Zi
–V
GG
+
Self-bias
bypassed RS
[JFET or D-MOSFET]
Self-bias +VDD
bypassed RS Medium (2 k) Medium (- 10)
[JFET or D-MOSFET] RD High (10 M)
C2
Vo = RD 储 r d = - gm(rd 储 RD)
C1 = RG
Vi
Zo ⬵ RD ⬵ - gmRD
(rd Ú 10 RD) (rd Ú 10 RD)

Zi
RG
RS CS

Self-bias
unbypassed RS
[JFET or D-MOSFET]
Low (- 2)
Self-bias +VDD RS
unbypassed RS c 1 + gmRS + dR
rd D gmRD
[JFET or D-MOSFET] RD High (10 M) = =
C2 RS RD RD + RS
Vo c 1 + gmRS + + d 1 + gmRS +
C1 = RG rd rd rd
Vi
Zo
= RD gmRD
Zi rd Ú 10 RD or rd =   ⬵ -
RG 1 + gmRS 3 rd Ú 10 (RD + RS)4
RS

Voltage-divider bias
[JFET or D-MOSFET]
Voltage-divider bias +VDD
[JFET or D-MOSFET]
Medium (2 k) Medium (- 10)
RD High (10 M)
C2
R1
Vo = RD 储 r d = - gm(rd 储 RD)
C1
Vi = R1 储 R2
Zo ⬵ RD ⬵ - gmRD (rd Ú 10 RD)
(rd Ú 10 RD)
Zi
R2
RS CS

514
 TABLE 8.1
(Continued)

Configuration Zi Zo Vo
Av =
Vi
Common-gate
[JFET or D-MOSFET]
Medium (+ 10)
Common-gate +VDD Low (1 k⍀)
[JFET or D-MOSFET] Medium (2 k⍀) RD
RD r d + RD gmRD +
C1 Q1 C2 = RS 储 c d rd
1 + gmrd = RD 储 r d =
Vi Vo RD
1 +
⬵ RD rd
1
Zi RS Zo ⬵ RS 储 (Rd Ú 10 RD)

RG CS gm ⬵ gmRD
(rd Ú 10 RD) (rd Ú 10 RD)

Source-follower
[JFET or D-MOSFET]
Low ( 6 1)
Source-follower Low (100 k⍀)
[JFET or D-MOSFET] +VDD
High (10 M⍀) gm(rd 储 RS)
C1 = rd 储 RS 储 1>gm =
Vi 1 + gm(rd 储 RS)
C2 = RG
Zi RG
Vo ⬵ RS 储 1>gm gmRS
RS
(rd Ú 10 RS)
⬵
Zo
1 + gmRS
(rd Ú 10 RS)

Drain-feedback bias
E-MOSFET
Drain-Feedback bias +VDD Medium (1 M⍀)
E-MOSFET Medium (2 k⍀) Medium (- 10)
RD RF + r d 储 RD
RF C2 = = RF 储 r d 储 RD = - gm(RF 储 rd 储 RD)
Vo 1 + gm(rd 储 RD)
C1
Vi RF ⬵ RD ⬵ - gmRD
(RF, rd Ú 10RD)
Zo ⬵ (RF, rd Ú 10RD)
1 + gmRD
Zi (rd Ú 10 RD)

Voltage-divider bias
E-MOSFET
Voltage-divider bias +VDD
E-MOSFET
Medium (2 k⍀) Medium (−10)
RD
C2 Medium (1 M⍀)
R1 D Vo
= RD 储 r d = - gm(rd 储 RD)
C1
G = R1 储 R2
Vi
Zo ⬵ RD ⬵ - gmRD
S (rd Ú 10 RD) (rd Ú 10 RD)
Zi R2 RS

515
516 FET AMPLIFIERS all the possible configurations are not present, the majority of the most frequently encoun-
tered are included. In fact, any configuration not listed will probably be some variation of
those appearing in the table, so at the very least, the listing will provide some insight as to
what expected levels should be and which path will probably generate the desired equa-
tions. The format chosen was designed to permit a duplication of the entire table on the
front and back of one 812 by 11 inch page.

8.14 EFFECT OF RL AND Rsig

●
This section will parallel Sections 5.16 and 5.17 of the BJT small-signal ac analysis chap-
ter dealing with the effect of the source resistance and load resistance on the ac gain of an
amplifier. There are again two approaches to the analysis. One can simply substitute the ac
model for the FET of interest and perform a detailed analysis similar to the unloaded situ-
ation, or apply the two-port equations introduced in Section 5.17.
All of the two-port equations developed for the BJT transistor apply to FET networks
also because the quantities of interest are defined at the input and output terminals and
not the components of the system.
A few of the most important equations are repeated below to provide an easy reference
for the analysis of this chapter and to refresh your memory about the conclusions:

RL
AvL = A (8.57)
RL + Ro vNL

Zi
Ai = -AvL (8.58)
RL

Avs =
Vo
=
Vi
# Vo
= a
Ri
ba
RL
bA (8.59)
Vs Vs Vi Ri + Rsig RL + Ro vNL

Some of the important conclusions about the gain of BJT transistor configurations are
also applicable to FET networks. They include the following facts:
The greatest gain of an amplifier is the no-load gain.
The loaded gain is always less than the no-load gain.
A source impedance will always reduce the overall gain below the no-load or
loaded level.
In general, therefore,

AvNL 7 AvL 7 AvS (8.60)

Recall from Chapter 5 that some BJT configurations are such that the output impedance
is sensitive to the source impedance or the input impedance is sensitive to the applied load.
For FET networks, however:
Due to the high impedance between the gate terminal and the channel, one can gener-
ally assume that the input impedance is unaffected by the load resistor and the output
impedance is unaffected by the source resistance.
One must always be aware, however, that there are special situations where the above
may not be totally true. Take, for instance, the feedback configuration that results in a direct
connection between input and output networks. Although the feedback resistor is usually
many times that of the source resistance, permitting the approximation that the source
resistance is essentially 0 , it does present a situation where the source resistance could
possibly affect the output resistance or the load resistance could affect the input impedance.
In general, however, due to the high isolation provided between the gate and the drain or
source terminals, the general equations for the loaded gain are less complex than those
encountered for BJT transistors. Recall that the base current provided a direct link between
input and output circuits of any BJT transistor configuration.
 To demonstrate each approach, let us examine the self-bias configuration of Fig. 8.45 EFFECT OF R L AND R sig 517
with a bypassed source resistance. Substituting the ac equivalent model for the JFET results
in the configuration of Fig. 8.46.

VDD

RD

D +
C2
G
+
Rsig C1 Zo
+ S RL V
o
Vs Vi RG
– Zi RS CS
– –

FIG. 8.45
JFET amplifier with Rsig and RL.

Note that the load resistance appears in parallel with the drain resistance and the source
resistance Rsig appears in series with the gate resistance R. For the overall voltage gain the
result is a modified form of Eq. (8.21):

Vo
AvL = = -gm(rd 储 RD 储 RL) (8.61)
Vi

G D

Rsig + + +
+ Zi
Zo
Vs RG gmVgs rd RD RL
Vi Vgs Vo
–
– – S –

FIG. 8.46
Network of Fig. 8.45 following the substitution of the ac equivalent circuit for the JFET.

The output impedance is the same as obtained for the unloaded situation without a source
resistance:

Zo = rd 储 RD (8.62)

The input impedance remains as

Zi = RG (8.63)

For the overall gain AvS,

RGVS
Vi =
RG + Rsig
518 FET AMPLIFIERS and

AvS =
Vo
= # = c RG d [-gm(rd 储 RD 储 RL)]
Vi Vo
(8.64)
Vs Vs Vi RG + Rsig

which for most applications where RG W Rsig and RD 储 RL V rd results in

AvS ⬵ -gm(RD 储 RL) (8.65)

If we now turn to the two-port approach for the same network, the equation for the overall
gain becomes
RL RL
AvL = AvNL = [-gm(rd 储 RD)]
RL + Ro RL + Ro
but Ro = RD 储 rd,
RL (rd 储 RD)(RL)
so that AvL = [-gm(rd 储 RD] = -gm
RL + RD 储 rd (rd + RD) + RL
and AvL = -gm(rd 储 RD 储 RL)
matching the previous result.
The above derivation was included to demonstrate that the same result will be obtained
using either approach. If numerical values for Ri, Ro, and AvNLwere available, it would
simply be a matter of substituting the values into Eq. (8.57).
Continuing in the same manner for the most common configurations results in the equa-
tions of Table 8.2.

8.15 CASCADE CONFIGURATION

●
The cascade configuration introduced in Chapter 5 for BJTs can also be used with JFETs
or MOSFETs, as shown for JFETs in Fig. 8.47. Recall that the output of one stage appears
as the input for the following stage. The input impedance for the second stage is the load
impedance for the first stage.
The total gain is the product of the gain of each stage including the loading effects of
the following stage.
Too often, the no-load gain is employed and the overall gain is an unrealistic result. For
each stage the loading effect of the following stage must be included in the gain calcula-
tions. Using the results of the previous sections of this chapter results in the following
equation for the overall gain of the configuration of Fig. 8.47:

Av = Av1Av2 = (-gm1RD1)(-gm2RD2) = gm1gm2 RD1RD2 (8.66)

FIG. 8.47
Cascaded FET amplifier.
518
 TABLE 8.2

Configuration AvL ⴝ Vo 储 Vi Zi Zo

- gm(RD 储 RL) RG RD

+
Vss Including rd:
–
- gm(RD 储 RL 储 rd) RG RD 储 r d

- gm(RD 储 RL) RG RD
1 + gmRS 1 + gmRS

Including rd:
+
Vs - gm(RD 储 RL) RD
– RG ⬵
RD + RS 1 + gmRS
1 + gmRS +
rd

- gm(RD 储 RL) R 1 储 R2 RD

+
Vs Including rd:
–
- gm(RD 储 RL 储 rd) R 1 储 R2 RD 储 r d ;

gm(RS 储 RL) RG RS 储 1>gm

1 + gm(RS 储 RL)

+ Including rd:
Vs RS
– gmrd(RS 储 RL) gmrdRS
= RG 1 +
rd + RD + gmrd (RS 储 RL) r d + RD

gm(RD 储 RL) RS RD
1 + gmRS
+
Including rd: RS
Vs Zi = RD 储 r d
– gmrdRS
⬵ gm(RD 储 RL) 1 +
r d + RD 储 RL

519
520 FET AMPLIFIERS The input impedance of the cascade amplifier is that of stage 1,

Zi = RG1 (8.67)
and the output impedance is that of stage 2,

Zo = RD2 (8.68)
The main function of cascading stages is the larger overall gain achieved. Since dc bias and
ac calculations for a cascade amplifier follow those derived for the individual stages, an
example will demonstrate the various calculations to determine dc bias and ac operation.

EXAMPLE 8.16 Calculate the dc bias, voltage gain, input impedance, output impedance,
and resulting output voltage for the cascade amplifier shown in Fig. 8.48.

+20 V

2.4 kΩ 2.4 kΩ

D Vo
0.05 μF D 0.05 μF

Vi G IDSS = 10 mA
VP = −4 V G IDSS = 10 mA
10 mV
0.05 μF VP = −4 V

S S
3.3 MΩ 3.3 MΩ
+ +
680 Ω 100 μF 680 Ω 100 μF

FIG. 8.48
Cascade amplifier circuit for Example 8.16.

Solution: Both amplifier stages have the same dc bias. Using dc bias techniques from
Chapter 7 results in
2IDSS 2(10 mA)
VGSQ = -1.9 V, IDQ = 2.8 mA gm0 = = = 5 mS
0 VP 0 0 -4 V 0
and at the dc bias point,
VGSQ -1.9 V
gm = gm0 a 1 - b = (5 mS)a 1 - b = 2.6 mS
VP -4 V
Since the second stage is unloaded

Av2 = -gmRD = -(2.6 mS)(2.4 k⍀) = ⴚ6.24

For the first stage 2.4 k⍀ 储 3.3 M⍀ ⬵ 2.4 k⍀ resulting in the same gain.
The cascade amplifier voltage gain is

Eq. (8.66): Av = Av1Av2 = (-6.2)(-6.2) = 38.4

Take special note of the fact that the total gain is positive.
The output voltage is then
Vo = AvVi = (38.4)(10 mV) = 384 mV
The cascade amplifier input impedance is TROUBLESHOOTING 521
Zi = RG = 3.3 M⍀
The cascade amplifier output impedance (assuming that rd  Æ) is
Zo = RD = 2.4 k⍀

A combination of FET and BJT stages can also be used to provide high voltage gain and
high input impedance, as demonstrated by the next example.

EXAMPLE 8.17 For the cascade amplifier of Fig. 8.49, use the dc bias calculated in
Examples 5.15 and 8.16 to calculate input impedance, output impedance, voltage gain, and
resulting output voltage.

+20 V

2.4 kΩ 15 kΩ 2.2 kΩ
0.5 μF
D C Vo
0.5 μF
Vi G B
1 mV IDSS = 10 mA β = 200
0.05 μF VP = −4 V
S E

3.3 MΩ + 4.7 kΩ +
680 Ω 100 μF 1 kΩ 100 μF

FIG. 8.49
Cascaded JFET-BJT amplifier for Example 8.17.

Solution: Since Ri (stage 2) = 15 k 储 4.7 k 储 200(6.5 ) = 953.6 , the gain of

stage 1 (when loaded by stage 2) is
Av1 = -gm[RD 储 Ri (stage 2)]
= -2.6 mS(2.4 k 储 953.6 ) = -1.77
From Example 5.18, the voltage gain of stage 2 is Av2 = -338.46. The overall voltage
gain is then
Av = Av1Av2 = (-1.77)(-338.46) = 599.1
The output voltage is then
Vo = AvVi = (599.1)(1 mV) ⬇ 0.6 V
The input impedance of the amplifier is that of stage 1,
Zi = 3.3 M⍀
and the output impedance is that of stage 2,
Zo = RD = 2.2 k⍀

8.16 TROUBLESHOOTING
●
As mentioned before, troubleshooting a circuit is a combination of knowing the theory
and having experience using meters and an oscilloscope to check the operation of the
circuit. A good troubleshooter has a sense for what to check based on the behavior of
the networks. This ability is developed through building, testing, and repairing a wide
522 FET AMPLIFIERS variety of configurations. For any small-signal amplifier one might consider the follow-
ing steps:
1. Look at the circuit board to see if any obvious problems can be seen: an area charred by
excess heating of a component; a component that feels or seems too hot to touch; what
appears to be a poor solder joint; any connection that appears to have come loose.
2. Use a dc meter: make some measurements as marked in a repair manual containing
the circuit schematic diagram and a listing of test dc voltages.
3. Apply a test ac signal: measure the ac voltages starting at the input and work along
toward the output.
4. If the problem is identified at a particular stage, the ac signal at various points should
be checked using an oscilloscope to see the waveform, its polarity, amplitude, and
frequency, as well as any unusual waveform “glitches” that may be present. In par-
ticular, observe that the signal is present for the full signal cycle.

Possible Symptoms and Actions

In the absence of an output ac voltage:
1. Check whether the supply voltage is properly connected.
2. Check whether the output voltage at VD is in the midrange between 0 V and VDD.
3. Check whether there is any input ac signal at the gate terminal.
4. Check the ac voltage at each side of the coupling capacitor terminals.
When building and testing an FET amplifier circuit in the laboratory:
1. Check the color code of resistor values to be sure that they are correct. Even better,
measure the resistor values because components used repeatedly may get overheated
when used incorrectly, causing the nominal value to change.
2. Check that all dc voltages are present at the component terminals. Be sure that all
ground connections are made common.
3. Measure the ac input signal to be sure the expected value is provided to the circuit.

8.17 PRACTICAL APPLICATIONS

●
Three-Channel Audio Mixer
The basic components of a three-channel JFET audio mixer are shown in Fig. 8.50. The
three input signals can come from different sources such as a microphone, a musical instru-
ment, background sound generators, and so on. All signals can be applied to the same gate
terminal because the input impedance of the JFET is so high that it can be approximated by
C1
v1
10 ␮F R4 20 V
R1
1 M⍀ 100 k⍀
R7 3.3 k⍀
C2 C5
v2 D vo
10 ␮F R5 10 ␮F
R2
IDSS = 10 mA
1 M⍀ 100 k⍀ G VP = –6 V
+
S
C3
v3 vG R8 C4 20 ␮F
10 ␮F 1 k⍀
R6
R3
1 M⍀ 100 k⍀ –

Volume control Signal-isolation Preamplifier

resistors gm ~
= 1.5 mS
Av = –4.95

FIG. 8.50
Basic components of a three-channel JFET audio mixer.
an open circuit. In general, the input impedance is 1000 M⍀ (109 ⍀) or better for PRACTICAL 523
JFETs and 100 million M⍀ (1014 ⍀) or better for MOSFETs. If BJTs were employed APPLICATIONS
instead of JFETs, the lower input impedance would require a transistor amplifier for each
channel or at least an emitter-follower as the first stage to provide a higher input impedance.
The 10-mF capacitors are there to prevent any dc biasing levels on the input signal from
appearing at the gate of the JFET, and the 1-M⍀ potentiometers are the volume controls for
each channel. The need for the 100-k⍀ resistors for each channel is less obvious. Their pur-
pose is to ensure that one channel does not load down the other channels and severely reduce
or distort the signal at the gate. For instance, in Fig. 8.51a, one channel has a high-impedance
(10-k⍀) microphone, whereas another channel has a low-impedance (0.5-k⍀) guitar ampli-
fier. Channel 3 is left open, and the 100-k⍀ isolation resistors have been removed for the
moment. Replacing the capacitors by their short-circuit equivalent for the frequency range of
interest and ignoring the effects of the parallel 1-M⍀ potentiometers (set at their maximum
value) result in the equivalent circuit of Fig. 8.51b at the gate of the JFET amplifier. Using
the superposition theorem, we determine the voltage at the gate of the JFET by
0.5 k⍀(vmic) 10 k⍀(vguitar)
vG = +
10.5 k⍀ 10.5 k⍀
= 0.047vmic + 0.95vguitar ⬵ vguitar

High- C1
impedance
microphone 10 ␮F
Rm 10 k⍀

+ 1 M⍀
vmic

– C2 vG vG
vG R4 R5
100 k⍀ 100 k⍀
Low- 10 ␮F Rm 10 k⍀ Rg 0.5 k⍀
110 k⍀ 100.5 k⍀
impedance Rg 0.5 k⍀
guitar + + Rm 10 k⍀ Rg 0.5 k⍀
1 M⍀
+ vmic vguitar
+ +
vguitar – – vmic vguitar
– – –

(a) (b) (c)

FIG. 8.51
(a) Application of a high- and a low-impedance source to the mixer of Fig. 8.50; (b) reduced equivalent without
the 100-k isolation resistors; (c) reduced equivalent with the 100-k resistors.

clearly showing that the guitar has swamped the signal of the microphone. The only re-
sponse of the amplifier of Fig. 8.51 will be to the guitar. Now, with the 100-k resistors in
place, the situation of Fig. 8.51c results. Using the superposition theorem again, we obtain
the following equation for the voltage at the gate:
101 k(vmic) 110 k(vguitar)
vG = +
211 k 211 k
⬵ 0.48vmic + 0.52vguitar vG

showing an even balance in the signals at the gate of the JFET. In general, therefore, the Rm Rg
100-k⍀ resistors compensate for any difference in signal impedance to ensure that
+ +
one does not load down the other and develop a mixed level of signals at the amplifier. vmic is vguitar >> vmic
Technically, they are often called “signal isolation resistors.” – –
An interesting consequence of a situation such as described in Fig. 8.51b is depicted in
pmic = vmic is
Fig. 8.52, where a guitar of low impedance has a signal level of about 150 mV, whereas the
microphone, having a larger internal impedance, has a signal strength of only 50 mV. As FIG. 8.52
pointed out above, the major part of the signal at the “feed” point (vG) is that of the guitar. Demonstrating that for parallel
The resulting direction of current and power flow is unquestionably from the guitar to the signals, the channel with the least
microphone. Furthermore, since the basic construction of a microphone and a speaker internal impedance and most power
is quite similar, the microphone may be forced to act like a speaker and broadcast the controls the situation.
guitar signal. New acoustic bands often face this problem as they learn the rudiments of
524 FET AMPLIFIERS good amplifier basics. In general, for parallel signals, the channel with the least internal
impedance controls the situation.
In Fig. 8.50, the gain of the self-biased JFET is determined by gmRD, which for this
situation is
-gm RD = (-1.5 mS)(3.3 k) = ⴚ4.95
For some it may come as quite a surprise that a microphone can actually behave like a
speaker. However, the classical example of the use of one voice cone to act as a microphone
and a speaker is in the typical intercom system such as appearing in Fig. 8.53a. The 8 , 0.2 W
speaker of Fig. 8.53b can be used as a microphone or a speaker, depending on the position of
the activation switch. It is important to note, however, as in the microphone–guitar example
above, that most speakers are designed to handle reasonable power levels, but most micro-
phones are designed to simply accept the voice-activated input, and they cannot handle the
power levels normally associated with speakers. Just compare the size of each in any audio
system. In general, a situation such as described above, where the guitar signal is heard
over the microphone, will ultimately damage the microphone. For an intercom system the
speaker is designed to handle both types of excitation without difficulty.

8, 0.2W
speaker

Proteomics
transformer

0.022F
capacitors

4-diode
bridge network
Capacitors

Resistor
banks
120 V power
cord
Slide rheostat
volume control
386D JRC
low-voltage audio
power amplifier

Lock NXP
HEF4069UB
Call Hex inverter
Talk
Volume
control
Channel LED LED in use 5670 JRC Switches
Channel select LEDs: in use selector power LED controller
A or B & power

(a) (b)

FIG. 8.53
Two-station, two channel intercom: (a) external appearance; (b) internal construction.
(Photos by Dan Trudden/Pearson).

Silent Switching
Any electronic system that incorporates mechanical switching such as shown in Fig.
8.54 is prone to developing noise on the line that will reduce the signal-to-noise ratio.
When the switch of Fig. 8.54 is opened and closed, one often gets an annoying “pfft, pfft”
sound as part of the output signal. In addition, the longer wires normally associated with

Noise RF

R1
v1 –
vo
Noise +
R2
v2

Mechanical switching

FIG. 8.54
Noise development due to mechanical switching.
mechanical switches will require that the switch be as close to the amplifier as possible to PRACTICAL 525
reduce the noise pickup on the line. APPLICATIONS
One effective method to essentially eliminate this source of noise is to use electronic
switching such as shown in Fig. 8.55a for a two-channel mixing network. Recall from
Chapter 7 that the drain to source of a JFET for low values of VDS can be looked on as a

R1

RDS RF

47 k⍀ 47 k⍀
v1 –
741 vo
Q1
+
1 M⍀
–RF
ON = 0 V vo = v
R1 i
OFF = –10 V 47 nF

47 k⍀
v2 Q1, Q2 = 2N3819

Q2
1 M⍀
ON = 0 V
OFF = –10 V 47 nF

(a)

RF
vTh = 1 v1 + 1 v2
2 2
RDS1 RTh 47 k⍀
v1 vTh –
47 k⍀ 100 ⍀ ~ 23.5 k⍀
= vo
+
RDS2 47.1 k⍀ 47.1 k⍀
v2
47 k⍀ 100 ⍀
+ + vo =
–RF
v
v1 v2 RTh i
47 k⍀ 1 v + 1v
– – =– ( 23.5 k⍀ ) ( 2 1 2 2 )
= –2 ( 1 v1 + 1 v2 )
Thévenin 2 2
vo = –v1 – v2
vTh = 1 v1 + 1 v2
2 2 or vo = –(v1 + v2)
RTh = 47.1 k⍀ =~ 23.5 k⍀
2

(b)

RF

R1 = 47.1 k⍀ 47 k⍀
47 k⍀ RDS1
v1 –
100 ⍀
vo
47 k⍀ +
v2

RF 47 k⍀ ~ –v
vo = – —–v = – ————v =
R1 i 47.1 k⍀ i i

(c)

FIG. 8.55
Silent switching audio network: (a) JFET configuration; (b) with both signals present; (c) with one signal on.
526 FET AMPLIFIERS resistance whose value is determined by the applied gate-to-source voltage as described in
detail in Section 7.13. In addition, recall that the resistance is the least at VGS = 0 V and the
highest near pinch-off. In Fig. 8.55a, the signals to be mixed are applied to the drain side of
each JFET, and the dc control is connected directly to the gate terminal of each JFET. With
0 V at each control terminal, both JFETs are heavily “on,” and the resistance from D1 to
S1 and from D2 to S2 is relatively small, say, 100  for this discussion. Although 100  is
not the 0  assumed with an ideal switch, it is so small compared to the series 47-k resis-
tor that it can often be ignored. Both switches are therefore in the “on” position, and both
input signals can make their way to the input of the inverting amplifier (to be introduced in
Chapter 10) as shown in Fig. 8.55b. In particular, note that the chosen resistor values result
in an output signal that is simply an inversion of the sum of the two signals. The amplifier
stage to follow will then raise the summation to audio levels.
Both electronic switches can be put in the “off” state by applying a voltage that is more
negative than the pinch-off level as indicated by the 10 V in Fig. 8.55a. The level of “off”
resistance can approach 10,000 M, which certainly can be approximated by an open
circuit for most applications. Since both channels are isolated, one can be “on” while the
other is “off.” The speed of operation of a JFET switch is controlled by the substrate (those
due to the device construction) and stray capacitance levels and the low “on” resistance of
the JFET. Maximum speeds for JFETs are about 100 MHz, with 10 MHz being more
typical. However, this speed is critically reduced by the input resistance and capacitance of
the design. In Fig. 8.55a, the 1-M resistor and the 47-nF capacitors have a time constant
of t = RC = 47 ms = 0.047 s for the dc charging network that is controlling the voltage
at the gate. If we assume two time constants to charge to the pinch-off level, the total time
is 0.094 s, or a switching speed of 1>0.094 s ⬵ 10.6 per second. Compared to the typical
switching speed of the JFET at 10 million times in 1 s, this number is extremely small.
Keep in mind, however, that the application is the important consideration, and for a typical
mixer, switching is not going to occur at speeds greater than 10.6 per second unless we have
some radical input signals. One might ask why it is necessary to have the RC time constant
at the gate at all. Why not let the applied dc level at the gate simply control the state of
the JFET? In general, the RC time constant ensures that the control signal is not a spurious
one generated by noise or “ringing” due to the sharply rising and falling applied pulses at the
gate. By using a charging network, we ensure that the dc level must be present for a period
of time before the pinch-off level is reached. Any spike on the line will not be present long
enough to charge the capacitor and switch the state of the JFET.
It is important to realize that the JFET switch is a bilateral switch. That is, signals
in the “on” state can pass through the drain–source region in either direction. This,
of course, is the way ordinary mechanical switches work, which makes it that much
easier to replace mechanical switch designs with electronic switches. Remember that
the diode is not a bilateral switch because it can conduct current at low voltages in only
one direction.
It should be noted that because the state of the JFETs can be controlled by a dc level,
the design of Fig. 8.55a lends itself to remote and computer control for the same reasons
described in Chapter 7 when dc control was discussed.
The data sheet for a low-cost JFET analog switch is provided in Fig. 8.56. Note under the
heading Drain Cutoff Current that the pinch-off voltage VGS  VP is typically about 10 V
at a drain-to-source voltage of 12 V. In addition, a current level of 10 nA is used to define the
pinch-off level. The level of IDSS is 15 mA, whereas the drain-to-source resistance is quite
low at 150  with VGS  0 V. The turn-on time is quite small at 10 ns (td + tr), whereas
the turn-off time is 25 ns.

Phase-Shift Networks
Using the voltage-controlled drain-to-source resistance characteristic of a JFET, we can
control the phase angle of a signal using the configurations of Fig. 8.57. The network of
Fig. 8.57a is a phase-advance network, which adds an angle to the applied signal,
whereas the network of Fig. 8.57b is a phase-retard configuration, which creates a nega-
tive phase shift.
 PRACTICAL 527
APPLICATIONS

FIG. 8.56
Specification sheet for a low-cost analog
JFET current switch.
(Copyright of Semiconductor Components Industries, LLC. Used by permission.)

RDS

+ + + D S +
C D –
VGS
+
vi G RDS vo vi G C vo
+ Control
VGS
Control – S
– – – –

(a) (b)

FIG. 8.57
Phase-shift networks: (a) advance; (b) retard.
528 FET AMPLIFIERS For example, let us consider the effect of RDS on an input signal having a frequency such
as 10 kHz if we apply it to the network of Fig. 8.57a. For discussion, let us assume that
the drain-to-source resistance is 2 k due to an applied gate-to-source voltage of 3 V.
Drawing the equivalent network results in the general configuration of Fig. 8.58. Solving
for the output voltage results in
RDS⬔0 Vi⬔0 RDSVi⬔0
Vo = =
RDS - j XC XC
2RDS 2
+ X C2 ⬔ - tan-1
RDS
RDSVi X R XC
⬔tan-1 b Vi ⬔tan-1
C DS
= = a
2RDS 2
+ XC2 RDS 2RDS2
+ X C2 RDS
so that
Vo = k1Vi ⬔u1
where

RDS XC
k1 = and u1 = tan-1 (8.69)
2R DS +
2
X C2 RDS

Substituting the numerical values from above results in

1 1
XC = = = 1.592 k
2pfC 2p(10 kHz)(0.01 mF)
RDS 2 k
and k1 = = = 0.782
2R DS +
2
X 2C 2(2 k) + (1.592 k)2
2

XC 1.592 k
with u1 = tan-1 = tan-1 = tan-1 0.796 = 38.52
RDS 2 k
so that Vo = 0.782Vi ⬔38.52
and an output signal that is 78.2% of its applied signal but with a phase shift of 38.52°.

vi C vo
Vi + + 0.78Vi
0.01 ␮F
180° 360°
Vi RDS 2 k⍀ Vo
0 90° ␪ –180° 0° 180° 360° ␪

– –
38.52°

FIG. 8.58
RC phase-advance network.

In general, therefore, the network of Fig. 8.57a can introduce a positive phase shift ex-
tending from a few degrees (with XC relatively small compared to RDS) to almost 90° (with
XC relatively large compared to RDS). Keep in mind, however, that for fixed values of RDS,
as the frequency increases, XC will decrease and the phase shift will approach 0°. For de-
creasing frequencies and a fixed RDS, the phase shift will approach 90°. It is also important
to realize that for a fixed RDS, an increasing level of XC results in diminishing magnitude for
Vo. For such a network, a balance between gain and desired phase shift will have to be made.
For the network of Fig. 8.57b, the resulting equation is

Vo = k2Vi⬔u2 (8.70)

where
XC RDS
k2 = and u2 = -tan-1
2RDS
2
+ XC2 XC
Motion-Detection System PRACTICAL 529
APPLICATIONS
The basic components of a passive infrared (PIR) motion-detection system are shown in
Fig. 8.59. The heart of the system is the pyroelectric detector, which generates a voltage
that varies with the amount of incident heat. It filters out all but the infrared radiation
from a particular area and focuses the energy onto a temperature-sensing element. Recall
from Chapter 7, Section 7.13, that the infrared band is a nonvisible band just below the
visible light spectrum. Passive detectors do not emit a signal of any kind but simply
respond to the energy flow of the environment.

VDD

RD

Alarm
C Controller/ system,
Low-frequency Comparator counter,
amplifier network driver
+ network
light
control,
RG etc.
vS RS

–
Infrared Parabolic Pyroelectric
heat optical element
filter

FIG. 8.59
Passive infrared (PIR) motion-detection system.

An external and an internal view of a commercially available unit are provided in Fig.
8.60a and b, respectively. Four interchangeable lens are provided for different coverage
areas. For our purposes the “pet” option was selected with the coverage indicated in Fig.
8.60c. The unit is mounted at a height of 7⬘6⬙ and operates at a dc voltage of 8.5 V to 15.4 V,
drawing a current of 17 mA at 12 V dc. The range of coverage is 35⬘ perpendicular to the
sensor and 20⬘ to each side. In the lowest sensitivity setting the combined weight of the
animals cannot exceed 80 lbs.
To focus the incident ambient heat on the pyroelectric detector, the unit of Fig. 8.60
uses a parabolic deflector. As a person walks past a sensor, he or she will cut the various
fields appearing in Fig. 8.60c, and the detector will sense the rapid changes in heat level.
The result is a changing dc level akin to a low-frequency ac signal of relatively high
internal impedance appearing at the gate of the JFET. One might then ask why turning
a heating system on or turning on a lamp doesn’t generate an alarm signal since heat will be
generated. The answer is that both will generate a voltage at the detector that grows steadily
with increasing heat level from the heating system or the burning bulb. Remember that for
the lamp, the detector is heat sensitive and not light sensitive. The resulting voltage is not
oscillating between levels, but simply climbing in level and will not set off the alarm—a
varying ac voltage will not be generated by the pyroelectric detector!
Note in Fig. 8.59 that a JFET source-follower configuration was employed to ensure
a very high input impedance to capture most of the pyroelectric signal. It is then passed
through a low-frequency amplifier, followed by a peak-detecting network and a comparator
to determine whether the alarm should be set off. The dc voltage comparator is a network
that “captures” the peak value of the generated ac voltage and compares it to a known dc
voltage level. The output processor determines whether the difference between the two
levels is sufficient to tell the driver to energize the alarm.
530 FET AMPLIFIERS

Multichip
processor
IC providing
100 ␮F
Wide-angle bus protection
capacitor
lens
IR
47 ␮F Detector
capacitors
Control settings
A4 DIP switch
microprocessor
LED
display Voltage
regulator MOSFET optical
solid-state relay
LED
For external
wiring 0.01 ␮F
capacitors

(a) (b)

DETECTION PATTERNS 0 7' 13' 20' 27' 35'

20'
Top View 1
Wide Angle Pet Immune Lens 2
13' 12 3
0 7' 13' 20' 27' 35'
4 7'6''
Side View
7' 18 13
5 Pet Immune Lens
14 0
0 19 6
15 Look-Down* Lower Intermediate Long
20
7 18–20 12–17 1–11
7' 16
8 (c)
17 9
13'
10
11
20'

FIG. 8.60
Commercially available PIR motion-detection unit: (a) external appearance; (b) internal construction; (c) pet option coverage.
[Photos (a) and (b) by Dan Trudden/Pearson.]

8.18 SUMMARY
●
Important Conclusions and Concepts
1. The transconductance parameter gm is determined by the ratio of the change in
drain current associated with a particular change in gate-to-source voltage in the
region of interest. The steeper the slope of the ID-versus-VGS curve, the greater is the
level of gm. In addition, the closer the point or region of interest to the saturation
current IDSS, the greater is the transconductance parameter.
2. On specification sheets, gm is provided as yfs.
3. When VGS is one-half the pinch-off value, gm is one-half the maximum value.
4. When ID is one-fourth the saturation level of IDSS, gm is one-half the value at
saturation.
5. The output impedance of FETs is similar in magnitude to that of conventional
BJTs.
6. On specification sheets the output impedance rd is provided as 1 , yos. The more
horizontal the characteristic curves on the drain characteristics, the greater is the
output impedance.
 7. The voltage gain for the fixed-bias and self-bias JFET configurations (with a bypassed COMPUTER ANALYSIS 531
source capacitance) is the same.
8. The ac analysis of JFETs and depletion-type MOSFETs is the same.
9. The ac equivalent network for an enhancement-type MOSFET is the same as that
employed for JFETs and depletion-type MOSFETs. The only difference is the equa-
tion for gm.
10. The magnitude of the gain of FET networks is typically between 2 and 20. The self-
bias configuration (without a bypass source capacitance) and the source-follower
are low-gain configurations.
11. There is no phase shift between input and output for the source-follower and common-
gate configurations. Most others have a 180° phase shift.
12. The output impedance for most FET configurations is determined primarily by RD.
For the source-follower configuration it is determined by RS and gm.
13. The input impedance for most FET configurations is quite high. However, it is quite
low for the common-gate configuration.
14. When troubleshooting any electronic or mechanical system, always check the
most obvious causes first.

Equations
ID
gm = yfs =
VGS
2IDSS
gm0 =
0 VP 0
VGS
gm = gm0 c 1 - d
VP
ID
gm = gm0
A IDSS
1 VDS
rd = = `
yos ID VGS = constant
For JFET and depletion-type MOSFET configurations, see Tables 8.1 and 8.2.

8.19 COMPUTER ANALYSIS

●
PSpice Windows
JFET Fixed-Bias Configuration The first JFET configuration to be analyzed in the ac
domain will be the fixed-bias configuration of Fig. 8.61, using a JFET with VP  4 V
and IDSS  10 mA. The 10-M resistor was added to act as a path to ground for the
capacitor but is essentially an open circuit for the ac analysis. The J2N3819 n-channel
JFET from the EVAL library was used, and the ac voltage is to be determined at four dif-
ferent points for comparison and review.
The constant Beta is determined by
IDSS 10 mA
Beta = = = 0.625 mA>V2
0 VP 0 2
42V2
and is inserted in the Edit Model dialog box obtained by the sequence EDIT-PROPERTIES.
Vto is also changed to 4 V. The remaining elements of the network are set as described
for the transistor in Chapter 5.
An analysis of the network results in the printout of Fig. 8.62. The CIRCUIT
DESCRIPTION includes all the elements of the network along with their assigned nodes.
In particular, note that Vi is set at 10 mV at a frequency of 10 kHz and a phase angle of 0