Chap 5.

Field-Effect Transistor

FET: the current is controlled by an electric field applied perependicular to the semiconductor
surface and to the direction of current.
Metal-Oxide-Semiconductor (MOSFET)
Metal-Semiconductor FET (MESFET)

1.1 Structure

* Two-Terminal MOS structure with S/D grounded VG < 0

(1) apply a negative bias to the gate with respect to the substrate,
 induce an E-field with direction .
Negative charges will exist on top of the gate plate.
In Si substrate, the majority HOLEs will move toward SiO2/Si E
E
interface due to E-field appliction.
Holes accumulate near the SiO2/Si interface, “Accumulation”

VG > 0
(2) Apply a positive bias to the gate wrs the Si substrate.
 induce an E-field with direction .
Positive charges will exist on top of the metal plate.
In Si substrate, the majority HOLEs will repel from SiO2/Si
interface and leave negatively charged ions. (depletion) E
As VGS , E-field , minority Electrons are attracted to
SiO2/Si interface, “Inversion”

Threshold Voltage (VTH): defined as the applied gate voltage needed to create an inversion layer
in which the charge density = the conc. of majority carriers in Si substrate. In other words, V TH is
the gate voltage required to “turn on” the transistor.

1
 For nMOS, if VTH >0, enhancement mode; if VTH <0, depletion mode
For pMOS, if VTH>0, depletion mode; if VTH >0, enhancement mode,

* Transistor Structure
For VGS > 0 inversion layer is formed underneath the SiO2/Si interface
 n- channel region is formed and Connects the n+ source and n+ drain.
.
If VDS > 0,  a current can be generated between S and D. Since the carriers moving in the
channel are electrons, the MOSFET is called nMOS.

Similary, for PMOS, the carriers moving in the channel are “Holes”  n-Si substrate, P+ Source
and Drain.

(a) if VDS << VGS -VTH,

 the channel layer is almost constant
 ID  VDS

(b) as VDS , the voltage drop across the oxide

near the drain 
 the inversion charge density near the drain 
 the incremental conductance at the drain 
 the slope of ID versus VDS 

(c) As VDS  to VDS(sat) = VGS -VTH

the inversion charge density near the drain= 0
 the conductance at the drain =0
 the slope of ID versus VDS =0 (saturation)

(a) if VDS > VDS(sat), the point of zero inversion charge

moves toward Source
electrons enter the channel at the source, travel
through the channel toward the drain, and then
are injected into the depletion region, where they
are swept by the E-field to drain” Saturation”

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⚫ I-V Characteristics

If VGS < VTH, “CUT OFF”

IF VGS > VTH, “ON”,

 
For VDS < VDS(sat), “Nonsaturation”, I D = kn 2(VGS − VTH )VDS − VDS where kn= =
2 WnCox
2L

For VDS > VDS(sat), “Saturation” I D = kn VGS − VTH  independent of VDS

2

Note: the geometry, (W, L, or dox) is a variable in the design of MOSFETs

P-MOSFET and Complementary CMOS

Figure 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is
formed in a separate n-type region, known as an n well. Another arrangement is also
possible in which an n-type body is used and the n device is formed in a p well. Not shown
are the connections made to the p-type body and to the n well; the latter functions as the
body terminal for the p-channel device.
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Figure 4.14 The relative levels of the terminal voltages of the enhancement NMOS transistor
for operation in the triode region and in the saturation region.

Figure 4.14 The relative levels of the terminal voltages of the enhancement PMOS transistor
for operation in the triode region and in the saturation region.

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*Ckt Symbols and Conventions
nMOSFET:
enhancement mode: VTH >0, a channel can be formed when VGS > VTH>0
depletion mode: VTH <0, a channel exists even at VGS = 0, so a negative voltage must be
applied to th edepletion mode-nMOSFET to turn it off.

Enhancement mode depletion mode

Large signal equivalent ckt .
Body Effect
If Vsub-source = 0, VTH is a constant. If Vsub-source  0, VTH is dependent on Vsub-sourc by


VTH = VTHo +  2 F + VSB − 2 F 
For VSB = 0 V
Related to the doping concentration of the substrate
Body effect parameter

Subthreshold Conduction  iD
For an ideal MOSFET, ID = 0 when VGS < VTH.
In reality, ID  0 as VGS < VTH, and it is called
“ subthreshold conduction”.
 It is significant for IC since it will
cause extra “Power” dissipation.

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Breakdown
“Punchthrough” occurs when the drain voltage is
large enough for the depletion region around the
drain extend completely to the source terminal
 ID increase rapidly (Breakdown)

Table Summary of Important MOSFET equations

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Common Source Circuit
VTHP = -0.8 V,
kp = 0.2 mA/V2

VTH = 1 V,
kn = 0.1 mA/V2

Solution:
(1)
Solution: VG = (VDD − 0) 
R2
= 2.5V
(1) R1 + R2
R2 VSG = VS − VG = 5 − 2.5 = 2.5  VTH = 1V
VG = (V DD − 0)  = 2V  MOSFET is " ON" ,VDS ( sat) = VSG + VTH = 2.5 + ( −0.8) = 1.7V
R1 + R2
VGS = VG − V S = 2 − 0 = 2  VTH = 1V
(2) Assume in “Saturation” mode,
 I D = k p VSG + VTH  = 0.578mA
2
 MOSFET is " ON" ,V DS ( sat) = VGS − VTH = 1V
 VSD = VS − VD = 5 − I D RD = 0.655V  VDS ( sat) = 1.7V
(2) Assume in “Saturation” mode,
VDD − VDS " Not" in saturation,"Wrong assumption"
 I D = kn VGS − VTH  , Recall I D =
2

RD (3) Reassume in “Nonsaturation”

 I D = 0.1(2 − 1) = 0.1mA
2  
 I D = k p 2(VSG + VTH )VSD − VSD2 , VSD = VDD − I D RD

 VDS = 3V  VDS ( sat) = 1V 

 In saturation and I D = 0.1mA
 I D = k p 2  1.7(5 − 7.5  I D ) − (5 − 7.5  I D )
2

 I D = 0.515mA,VSD = 1.14V  VDS ( sat) = 1.7V
" Nonsaturation, " Right assumption"

MOS as an amplifier and switch

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How to choose Q

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Biasing in MOS amplifier circuit

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 Figure 4.30 Biasing using a fixed voltage at the gate, VG, and a resistance in the source lead,
RS: (a) basic arrangement; (b) reduced variability in ID; (c) practical implementation using a
single supply; (d) coupling of a signal source to the gate using a capacitor CC1; (e) practical
implementation using two supplies.
• A source resistor RS is usually used to stabilize the Q-point of MOSFET against variation in
transistor parameters: (L, W, Cox, VTH).

Solution:
VTH = 2 V,
R2
kn = 0.1 mA/V2 (1) VG = (VDD − 0)  = 5.24V
R1 + R2
10 k VS = I D RS
(2) Assume in “Saturation” mode,
 I D = kn VGS − VTH  = 0.1VG − VS − VTH 
2 2

 I D = 0.1(5.24 − 2 I D − 2) = 0.5mA
2

 VS = 1V ,VGS = = 4.24V ,VDS ( Sat) = VGS − VTH = 2.24V

 VDS = VDD - I D RD - I D RS = 4  2.24 = VDS ( Sat)
 In saturation and I D = 0.5mA
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An enhancement load (VTH > 0 for nMOS and VTH < 0 for pMOS)
If an enhancement load device is connected with a MOSFET driver, this circuit can be used as
an amplifier or as an inverter.
If an enhancement load is connected with G & D shorting
VG = VD VGS = VDS  VDS > VGS – VTH = VDS(sat)
 transistor must be in “saturation” if it is on.

Solution:
(iii) VI = 5 V,
 VGSD = 5 V, VDSD(sat) = VGSD –VTHD = 5-1 = 4V.
(iii) If MD is in saturation  VDSD> VDSD(sat) = 4V
 Possibility is “LOW”
(ii) Assume in MD “Nonsaturation”, (ML is known in “Sat”)
 MD and ML are in series, IDD = IDL.
 IDD=knD[2(VGSD – VTHD) VDSD – VDS2D] = IDL= knL(VGSL – VTHL)2
 VGSD = VI = 5 V, VDSD = VO, VGSL = VDSL =VDD – VO = 5- VO
(iii)  knD[2(VI – VTHD) VO – VO2] = IDL= knL(VDD – VTHL)2
 3 VO2 – 24VO + 8 = 0
 VO = 7.65 V (→,  VO must < 5 V) or 0.349 V
 VO = 0.349 V = VDSD < 4 V (Right assumption)
 ID = 133 A
(2) if VI = 1.5 V,
 VGSD = 5 V > VTHD, MD is ON and VDSD(sat) = VGSD - VTHD = 0.5V
MD is very possible in “Saturation”, while ML is known in “Sat”
(3)  IDD= IDL.
 IDD=knD(VGSD - VTHD)2 = knL(VGSL - VTHL)2
 VO = 3.64 V = VDSD > 0.5 V = VDSD(sat), “Right assumption”
 ID = 12.5 A
“1” VI = 5 V,  VO = 0.349 V “0”
“0” VI = 1.5 V,  VO = 3.64 V “1”

• Depletion Load (VTH < 0 for nMOS and VTH > 0 for pMOS)

VGS = 0 > VTH,  VTH < 0  transistor ML is always “ON”

Solution:
(1) VI = 5 V,
 VGSD = 5 V, VDSD(sat) = VGSD –VTHD = 5-1 = 4V.
(i) Assume in MD “Nonsaturation” and ML is in “Sat”
 MD and ML are in series, IDD = IDL.
 5 VO2 - 40VO + 4 = 0
 VO = 7.9 V (→,  VO must < 5 V) or 0.1 V
 VO = 0.1 V = VDSD < 4 V = VDSD(sat) (Right
assumption) 23
 IDD = IDL = 40 A
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• Constant-current source Biasing

Solution:
(1) M2, M3, and M4 form the const-current source!
(2) M4 :
VG4 = VD4,  VDS4 = VGS4 > VGS4 – VTH4
 M4 is in “Saturation”
(3) M3 : in “Saturation” for the same reason
(4) ID3 = ID4 = Iref
 kn3 (VGS3 - VTH3)2 = kn4(VGS4 - VTH4)2 equation (A)
(5)  VGS3 +VGS4 = 0 – V- = 5V equation (B)
kn 4
5 − VTH 4  + VTH 3
 kn3
VGS 3 = = 2.5VS
k
1 + n4
kn3
(6)  VGS3 = VGS2, assume M2 in “Saturation”
 IQ= kn2(VGS3 - VTH2)2 =0.225 mA
(7) for M1 : ID1 = IQ (assume in Saturation)
(7)  ID1 = 0.225 = kn1 (VGS1 - VTH1)2
 VGS1 = 2.06, VDS2 = VS1 – VS2 = 2.94 > VDS2(sat)
(Right assumption)

Amplifer
Consider an NMOS,

To get a linear amplification (Vo/Vi : linear), the MSOFET should be biased in saturation mode.
vGS = VGSQ (dc component) + vi (ac component)
 iD = kn(VGS – VTH)2 = kn(VGSQ + vi – VTH)2 = kn[(VGSQ – VTH) + vgs]2
 iD = kn(VGSQ – VTH)2+ 2kn(VGSQ – VTH)vi + knvi2
Generally, vi << 2(VGSQ – VTH) vi2 is much smaller and could be neglected
 iD = kn(VGSQ – VTH)2+ 2kn(VGSQ – VTH)vi

IDQ id =2kn(VGSQ – VTH)vgs  gmvgs

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  The small-signal drain current transconductance gm :
i d
gm  = 2k n (VGS − VTH ) = 2 k n I DQ  k n (W / L)
v gs
W , L  g m 
Note:
1. With the Q point in the saturation region, the transistor operates as a constant current
source that is linearly controlled by vgs.
2. The gm of MOSFETs tends to be small compared to that of BJTs. However, the
advantages of MOSFETs are:
(A) high input impedance
(B) Small size (high packing density)
(C) Low power consumption

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AC equivalent circuit of Common-Source amplifier

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Example: If R1 and R2 are biased the MOSFET in saturation mode,
and the signal frequency is large enough for CC acts as a
short circuit, the ac equivalent circuit becomes:

vo = -gmvgs (ro // RD)

vgs = vi
 Av = vo/vi = -gm (ro//RD)
Ri  vi/ii = R1//R2
Ro = vo/io |vi = 0 = ro //RD

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Common-Gate configuration (Input: source, gate: grounded)

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⚫ RG is used to prevent the buildup of static charge on the gate.
v
(1) vo = gmvgs (RD// RL), vgs = -vi ,  AV = o = g m ( RD // RL )
vi

(2) I O =
(− gmVgs )RD , I = − g V  A = Io = RD
RD + RL I i RD + RL
i m gs i

Vi − Vgs 1 V
(3) Rin = = = , Ro = x = RD
I i − g mVgs g m I x V =0
i

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Source-Follower Amplifier (Output is taken from the source terminal)

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(1) vo = gmvgs (RS//ro),
vo g ( R // r )
vi = vgs + vo = vgs [1+gm(RS//ro)]  AV = = m S o 1
v i 1 + g m ( RS // ro )
(1) Rin = R1//R2
(2) Ro = vo/io |vi = 0  vg = 0, vgs = -vS = -vo
vo vo v ( RS // ro )
(3) io = − g m vgs = + gm vo  Ro  o = = 1 // RS // ro
( RiS // ro ) ( RiS // ro ) io 1 + g m ( RS // ro ) gm

Note: although the voltage gain Av of a source follower < 1, but its output resistance Ro is very
small compared to that of a common-source circuit. A small Ro is desired when the circuit is to act
as an ideal voltage source a drive a load circuit without suffering loading effects.
⎯ similar to Emitter-follower

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Summary of Three Basic Amplifier Configurations
Configuration Voltage gain Current gain Rin Ro
Common-Source AV > 1 ⎯ 
Source-Follower AV  1 ⎯  Low
Common-Gate AV > 1 Ai ~ 1 Low (1/gm)

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MOSFET High-frequency Model

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CMOS Common-Source Amplifier

Small-Signal Equivalent Circuit:

W  V A1 V A2
g m1 = 2k n'   I REF , ro1 = , ro 2 =
 L 1 I REF I REF
W 
2k n'  
 L 1 1
AV = −
1 1 I REF
+
V A1 V A2

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CMOS Common-Gate Amplifier

(1) Replacing Q2 with its output resistance ro2

(2) For Q1, the source is not grounded,
a current source gm1vbs1 is included,
vbs1 = -vi

(1) Vgs1 = -vi, vbs1 = -vi

(2) For node D1 and D2,

vi − vo v  1
+ (gm1 + gmb1 )vi = o  Av = o =  gm1 + gmb1 + (ro1 // ro 2 )
v
ro1 ro 2 vi  ro1 

(3) Ri = vi/ii
(4) ii =(gm1 + gm2)vi +(vi - vo)/ro1

1  ro 2 
 Ri = 1 + 
(gm1 + gmb1 )  ro1 
⎯ lower than that of Common-source amplifier

Source Follower

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 (1) vo = gm1vgs1 RS
vi = vgs1 + vo = vgs1 [1+gm RS ]
v g R
 AV = o = m S  1
vi 1 + gm RS

Determine Ro, vi = 0, apply vx,

1 1
 Ro = // // ro1 // ro 2
g m1 g m 2

CMOS Inverter

vDSN 1
(1) vI = VDD “High”, rSDN = =
iDSN W 
i DSN → 0 kn'   (VDD − Vtn )
 L n

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 vDSP 1
(2) vI = 0 “Low”, rSDP = =
iSDP v W 
SDP→V DD kP'   (VDD + VtP )
 L P

+
VSGP
⎯

+
VGSN
⎯

The Voltage Transfer Characteristic (VTC)

W   1 
iDN = kn'   (vI − vTN )vo − vo2  for vo  vI − vtN
 L n  2 
1 W 
iDN = kn'   (vI − vTN ) for vo  vI − vtN
2
For QN,
2  L n
1 W 
where kn'   = kn
2  L n

W   
iDP = k P'   (VDD − vI − | vTP |)(VDD − vo ) − (VDD − vo )2  for vo  vI + | vtP |
1
 L P  2 
1 W 
iDP = k P'   (VDD − vI − | vTP |) for vo  vI + | vtP |
2
For QP,
2  L P
1 W 
where k P'   = k P
2  L P

The CMOS inverter is usually designed to have

(i) |VTN| = |VTP|
W 
 
 L  P = n
(ii) kn = kp (that is, kn’(W/L)n = kp’(W/L)p)
W  p
 
 L n

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 v o
Recall Chapter 1, VIL and VIH occur when = −1 , to determine VIH, we know that QN is in
v I
“triode” region, QP in “Saturation” region.

 i DN = i DP ,VTN = V DD − VT  (v I − VT )v o − v o = (V DD − v I − VT )
1 2 1 2

2 2
in whcih we substitute v I = V IH and dv O dt = −1 to obtain
V DD
v O = V IH −
2
Substituti ng v I = V IH , we can get V IH = 81 (5V DD − 2Vt )
Similarly, we can determine V IL by Q N is in " Sat." and Q P is in " Nonsat."
 V IL = 81 (3V DD + 2Vt )
The noise margins can now be determined as follows :
NM H = VOH − V IH
= V DD − 81 (5V DD − 2Vt )
= 81 (3V DD + 2Vt )
NM L = V IL − VOL
= 81 (3V DD + 2Vt ) − 0
= 81 (3V DD + 2Vt )

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Dynamic Operation
⎯ To determine the propagation delay of the inverter.
Assume a capacitor C (load) is connected between the output of the inverter and ground. Here C
represents the sum of the internal capacitors of next stages QN and QP.

Assume the circuit is symmetric (i.e., NMOS and PMOS are matched),  the rise time and fall
time of the output waveform should be equal.
(1) C is charged through QP from VDD (vI = 0, QN is OFF)

tPLH : is the time required that C is charged from 0 to VDD/2.

2C  Vt 1  3V − 4Vt 
tPLH =  + ln  DD 
' W  VDD − Vt 2  VDD
k P   (VDD − Vt )  
 L P

(2) C is discharged through QN to ground when vI is high, QP is OFF.

tPHL : is the time required for C to discharge from VDD to VDD/2.

2C  Vt 1  3V − 4Vt 
tPHL =  + ln  DD 
' W  VDD − Vt 2  VDD
kn   (VDD − Vt )  
 L n

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We know that in every cycle, ½CVDD2 of energy is dissipated in QN and ½CVDD2 dissipated in QP.
So if the inverter is witched at a frequency f  the dynamic power dissipated will be
PD = f CVDD2.
A figure of merit of a particular circuit technology is the “delay-power” product DP = PD • tP
It is observed that tP, PD, DP ~ constant.

•
• Digital Logic Gate:
(4) NMOS Inverter
(8) If VI < VTH,  M1 is “OFF”  ID = 0, VO = VDD.
(9) If VI > VTH,  M1 is “ON”  VO = VDD - ID RD
As VI , ID   VO
(3) VI “0”  VO “1”
VI “1”  VO “0”  “Inverter”

Power Dissipation
Consider the power dissipation in a MOSFET inverter with VDD = 5 V, RD = 10 , VTH = 0.8 V,
kn =0.3 A/V2.
If VI < VTH =0.8 V,  ID = 0, VO = VDD = 5V.  Power dissipated in the transistor is “zero”.
If VI = VTH =0.8 V, assume M1 is in “Nonsaturation”
 VO = VDD – knRD[2(VI – VTH)VO – VO2]
 3 VO2 –26.2 VO + 5 = 0
 VO = 0.195 or 8.54 (→,  VO must be less than VDD)
 ID = (VDD - VO)/RD = 0.48 A
the power dissipated in the MOSFET is
PT = ID • VDS = 0.48 x 0.195 = 93.6 mW
the power delivered to RD is
PRD = I2D • RD = 2.34 mW

Digital Logic Gate

V1 V2 VO
0V 0V “1”
5V 0V “0”
0V 5V “0”
5V 5V “0”
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MOSFET as an Analog Switch
⚫ Analog Switch
+
vO
_
An NMOS Analog Switch

As vC is low, the MOSFET is OFF,  Switch is “open”

As vC is high, the MOSFET is ON,  Switch is “closed”

A CMOS Transmission Gate

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 As the Gate is “Closed”

FIFTH EDITION 4.18, 4.26, 4.33, 4.37, 4.42, 4.47, 4.48, 4.53, 4.54, 4.61, 4.77, 4.86, 4.87, 4.92,
4.93, 4.101, 4.104

SEVENTH EDITION 5.22, 5.23, 5.26, 5.37, 5.39, 5.40, 5.43, 5.45, 5.46, 5.49, 5.50, 5.51, 5.52,
5.53, 5.54, 5.55, 5.56,

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