ECE 5545: Advanced VLSI

Lecture 0: Introduction

Paul K. Ampadu, Ph.D.

IC/ARI/CESCA/MICS
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 About Me
▪ Ph.D. ECE, Cornell 2004
▪ Energy-efficient 3G VLSI Turbo Codecs
▪ IBM Doctoral Fellowship ‘99—’04
▪ SRC Master’s Scholarship ‘97—’99

▪ University of Rochester 2004—2016

▪ MIT 2011—2013
▪ Virginia Tech 2016 —
▪ Professor & Assoc. Vice President of Diversity, VT IC
▪ IBM Research, Microsoft, Allied Telesyn
 About Me (2)
▪ Research Focus
▪ Reliable, Energy-efficient Networks-on-Chip (NoCs)
▪ Efficient VLSI Implementation of AI, ML, DSP Functions
▪ DSP/Info Theory Applications to Reliable IoT

▪ Teaching
▪ VLSI/ Electronics/Embedded Systems/ Computer Architecture
▪ Digital Communications/ Error Control Systems

▪ Some Notable Students

▪ D. Wolpert, Director IBM
▪ Q. Yu, Professor UNH & PD National Science Foundation
▪ D. Huo, Senior Manager Google Inc.
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▪ C. Li, Qualcomm
VLSI Chip Inside?

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Energy Efficiency through Multicore

Intel 80-Tile Processor1

• MAC/2D mesh

Intel (Single Cloud Chip) 48-Core2

• Pentium IA-32 cores Tilera TILE-Gx723
• 2D mesh • 64-bit uP per core/2D mesh
• 16KB L1-I &-D cache/256KB L2 • 23 MBs cache

[1] R. V. Sriram et al., “An 80-Tile Sub-100W TeraFLOPS Processor in 65-nm CMOS”, ISSCC, 2008.
[2] S. Dighe et al., “A 48-Core IA-32 message-passing process with DVFS in 45nm CMOS”, ISSCC, 2010. 5
[3] “Tilera Announces TILE-Gx72, the World’s Highest-Performance and Highest-Efficiency Manycore Processor,” http://www.tilera.com, 2013.
 The Heterogeneous NoC
▪ Towards a hybrid CMOS/Nano Network-on-Chip

NI NI
NanoCMOS IP BDT-based IP
R R

Your favorite NI NI
technology IP Link FinFET-based IP
R R
Gate

Source Drain

Copper Nanowire CNT Graphene 6

 Silicon Waveguides: Wires for Light
Total Internal Reflection Snell’s Law: n1Sin(1)=n2Sin(2)
• Light is confined in higher index material
when 1>c, the critical angle

Waveguides are a three-dimensional “wire” for light.

Waveguides enable complex devices:

Si
SiO2
450nm

Si
7 Splitter Ring Resonator Nanocavity Photonic Crystal
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SiO2
 Hybrid Photonic/Electronic NoC
Source Destination
Electronic Network Interface e-NoC Electronic Network Interface

Electronic Receive/Send Data Buffers Electronic Receive/Send Data Buffers

Modulator Driver Photodetector/ Photodetector/ Modulator Driver

Circuit Receiving Receiving Circuit
Circuitry p-NoC Circuitry

Electro-Optic Modulator Electro-Optic Modulator

Laser

▪ Electronic network manages reliability and path setup of overall network.

▪ Photonic network for communication between cores
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▪ Transfer large amounts of data with low power dissipation < 100fJ/bit.
 Nano-structured Devices
25 nm gate [IBM] 22 nm SRAM [IBM] Triple-gate device [Intel] Memristor [HP]

FinFET
Gate 3DCMOS Graphene CNT

Source Drain

Ballistic Rectifier 1 THz InP HEMT Quantum point contact BDT

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EdISon Books

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 Formal Course Description
▪ Advanced concepts in CMOS-based digital system
design. Topics include implementation of special
purpose structures for complex digital systems,
automation and verification of the design process,
and design for testability; design techniques for
low-power, power dissipation estimation, and
application of low-power techniques in the
different levels of the design hierarchy.
▪ Pre-Req: Basic knowledge of CMOS VLSI design
& analysis at ECE 4540 level/Tools/HDL
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2024 ECE 5545 Course Themes

▪Internet of Things
▪Adaptive Heterogeneous SoC
▪Low-Power Design
▪Trustworthy IoT
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 Why ECE5545?
▪ Design & Analysis of VLSI
▪ Technical Writing Skills
▪ Active Reading/Critique
▪ Independent/Teamwork
▪ Research Skills
▪ Presentation Skills
▪ Jobs/Research/MS-PhD
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 Why “Advanced”?
1. Advanced Low-Power Techniques
2. 3D-IC & Heterogeneous Integration
3. Smart/Reconfigurable, Adaptive ASICs
▪ e.g. Reconfigurable NoC Router

4. Clock Distribution
5. Power Distribution
6. Asynchronous & Self-Timed Design
7. Emerging Memories & Interconnects
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Annual Semiconductor Sales
▪ 1018 transistors manufactured in 2003
▪ 100 million for every human on the planet
Global Semiconductor Billings

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(Billions of US$)

150

100

50

0
1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002

Year

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Companies Hiring ECE 5545 Grads
Intel AMD

TI IBM

Google Sony

Samsung Toshiba

Micron Apple

Microsoft Qualcomm

Nvidia Broadcom 16
VLSI/IC Design US$185,000
Source: Electronic Design, Oct. 2008
electronicdesign.com

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Demographics
▪ International exposure

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http://webcaspar.nsf.gov
 Tentative Course Outline
1. CMOS & Combinational Circuit/Logic Review
• Logic Families/Tools/Logic Synthesis/VHDL, Verilog Review
2. Computer Systems Roadmaps
3. Sequential Circuit Design
4. Arithmetic Building Blocks
5. Interconnect
6. Clock & Power Distribution
7. Low Power Design
8. Memory & I/O Design
9. Reliability
10. New Directions e.g. 3D, IoT, etc.
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 Course Logistics
▪ Course Goal
Design, implement & optimize CMOS digital circuits &
systems w.r.t. different constraints, e.g. speed (latency &
throughput), power & energy dissipation, reliability, cost
(size & complexity), etc.
▪ Grading
▪ Group Leadership, Projects, Readings, Discussions, &
Presentations 60%
▪ Quizzes 10%
▪ Final Project 20%
▪ Attendance & Participation 10% 20
 Administrative Info
▪ Instructor: Dr. Paul Ampadu
▪ Office: ARL, 5-002
▪ Email: ampadu@vt.edu
▪ Office hours: By appointment
▪ Course web page: Canvas
▪ Graduate Helpers (TAs):
▪ Alberta Dadeboe, Ph.D. Student
▪ Study & Learning Groups
▪ Send (GTA) 1-page Resume Outlining VLSI Experience
▪ Focus on VLSI Tools, Analysis, ETC. 21
 Course Info
▪ Lectures
▪ M, W 4:00—5:15pm, Online
▪ Textbook (None, Research Literature ETC.)
▪ Neil Weste & David Harris, CMOS VLSI Design: A
Circuits & Systems Perspective (4ed.)
▪ Rabaey et al, Digital Integrated Circuits 2ed.
▪ Brunvand, Chip Design with Cadence/Synopsys
▪ Wolf, Modern VLSI Design

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 Project & Homework Policy
▪ Design Projects, Readings, Discussions, Presentations
& Assignments (60%)
▪ Design ICs using Cadence (Verilog, VHDL, etc.)
▪ Read & Critique Papers on Selected Topics
▪ Class Discussions Critical for Learning
▪ Late reports not allowed
▪ Concepts may be discussed together but …
▪ Solutions must be generated & submitted
independently or by team, as required per project
▪ Violations may result in academic referral
▪ Final group project (20%)
▪ May gradually build up over course of semester 23
 Final Project/Quizzes
▪ Builds over mini class projects
▪ Reinforce lecture & lab concepts
▪ Project Proposal Report & Presentation
▪ Final Project Report IEEE Format
▪ Final Project Presentation
▪ In-Class Quizzes reinforce lectures/readings

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Attendance & Participation Policy
▪ Class attendance critical
▪ Class participation necessary
▪ Paper discussions critical for learning
▪ Generates creative discussions
▪ Important questions help everybody
▪ Provides feedback on lectures & learning
▪ Attendance/Participation: 10%

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 Topic Leadership
1. Identify 3‒5 Most Important Topic Papers
▪ Citations & Forum Quality
▪ ISSCC, CICC, VLSI Symposium, DATE, DAC, ISCA, HPCA, NOCS,
Proc. IEEE, JSSC, TCAD, TVLSI, TCASI & II, JETCAS, IoT Magazine, …
▪ Timeliness e.g. 2020+
▪ Seminal? e.g. Bill Daly NoCs Idea paper
▪ Invited / Keynote / Special issue

2. Introduce Topic (20-30 min)

▪ What is it? Why important? Innovations?
▪ Details
▪ Implementations – How? Who? Related? Issues? Challenges? Future Topics?
▪ Comparisons & Results & Conclusions 26
 Final Project Examples
▪ Large-scale SRAM for Enhanced Resiliency
▪ Design of MPSoC Dynamic Task Scheduler
▪ Circuit Design for DRAM-SoC Interface
▪ Use available online SoC models
▪ Near-Threshold Cache Architecture
▪ Digital Frequency Synthesizer
▪ Distributed/Delayed Clock Generation SoC

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Assignment 0: Semiconductor History
▪ Vacuum Tubes –1st half of 20th century
▪ Large, expensive, power-hungry, unreliable
▪ 1947: First point contact transistor by John
Bardeen & Walter Brattain at Bell Labs
▪ 1949: Bipolar Transistor – W. Shockley
▪ 1958/59: First Monolithic IC (2T) – Jack Kilby TI
▪ 1960: 1st commercial IC – Fairchild (Intel folks)
▪ 1962-1990s: TTL
▪ 1974-1980s: ECL
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 Transistor Revolution
▪ 2003
▪ Intel Pentium-4 processor (55M transistors)
▪ 512 Mbit DRAM (> 0.5 billion transistors)
▪ 53% compound annual growth for 45 yrs
▪ No other technology has grown so fast so long
▪ Driven by miniaturization of transistors
▪ Smaller is cheaper, faster, lower in power!

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 Transistor Types
▪ Bipolar transistors
▪ npn or pnp silicon structure
▪ Small current into very thin base layer controls large
currents between emitter and collector
▪ Base currents limit integration density
▪ Metal Oxide Semiconductor FETs
▪ nMOS and pMOS MOSFETS
▪ Voltage applied to insulated gate controls current
between source and drain
▪ Low power allows very high integration 30
 MOSFET Technology
▪ MOSFET - Lilienfeld (Canada) in 1925 and Heil
(England) in 1935
▪ CMOS – 1960’s, but plagued by manufacturing
▪ PMOS in 1960’s (calculators)
▪ NMOS in 1970’s (4004, 8080) – for speed
▪ CMOS in 1980’s – preferred MOSFET technology
because of power benefits
▪ BiCMOS, Gallium-Arsenide, SiGe
▪ SOI, Copper-Low K, …
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 Why Silicon CMOS?
▪ Low power dissipation
▪ Significant only during switching (T or F???)
▪ High logic integration density
▪ Allows rail-to-rail output logic swings
▪ Provides symmetric transient response
▪ Capacitive nodes for dynamic storage
▪ Silicon technology (infrastructure) &
know-how (expertise)
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Technology Directions: SIA Roadmap
Year 1999 2002 2005 2008 2011 2014
Feature size (nm) 180 130 100 70 50 35
Mtrans/cm2 7 14-26 47 115 284 701
Chip size (mm2) 170 170-214 235 269 308 354
Signal pins/chip 768 1024 1024 1280 1408 1472
Clock rate (MHz) 600 800 1100 1400 1800 2200
Wiring levels 6-7 7-8 8-9 9 9-10 10
Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.6
High-perf power (W) 90 130 160 170 174 183

Battery power (W) 1.4 2.0 2.4 2.0 2.2 2.4

For Cost-Performance MPU (L1 on-chip SRAM cache; 32KB/1999 doubling every two years)
 Major Design Challenges
▪ Microscopic Issues ▪ Macroscopic Issues
▪ ultra-high speeds ▪ time-to-market
▪ power dissipation, supply rail ▪ design complexity
drop (millions of gates)
▪ growing importance of ▪ high levels of
interconnect abstractions
▪ noise, crosstalk ▪ reuse and IP, portability
▪ reliability, manufacturability ▪ systems on a chip (SoC)
▪ clock distribution ▪ tool interoperability

Year Tech. Complexity Frequency 3 Yr. Design Staff Costs

Staff Size
1997 0.35 13 M Tr. 400 MHz 210 $90 M
1998 0.25 20 M Tr. 500 MHz 270 $120 M
1999 0.18 32 M Tr. 600 MHz 360 $160 M
2002 0.13 130 M Tr. 800 MHz 800 $360 M 34
 Coping with Complexity
▪ How to design System-on-Chip?
▪ Billions of transistors
▪ Tens to hundreds of engineers
1. Structured Design
2. Design Partitioning

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 Structured Design
▪ Hierarchy: Divide and Conquer
▪ Recursively decompose system into modules
▪ Regularity
▪ Reuse modules wherever possible
▪ Ex: Standard cell library
▪ Modularity: well-formed interfaces
▪ Allows modules to be treated as black boxes
▪ Locality
▪ Physical and Temporal 36
 Design Partitioning
▪ Architecture: User’s perspective, what does it do?
▪ Instruction set, registers
▪ MIPS, x86, Alpha, PIC, ARM, …
▪ Microarchitecture
▪ Single cycle, multcycle, pipelined, superscalar?
▪ Logic: how are functional blocks constructed
▪ Ripple carry, carry lookahead, carry select adders
▪ Circuit: how are transistors used
▪ Complementary CMOS, pass transistors, domino
▪ Physical: chip layout
▪ Datapaths, memories, random logic 37
Questions?

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