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15/11/2023, 15:57 Digital IC back-end implementation | The difference between TSMC 12nm and TSMC 28nm Metal Stack - C…

Digital IC back-end implementation | The difference between TSMC 12nm and T


28nm Metal Stack
IC Pioneer Published on 2023-11-04 16:31:05 Reading volume 456 collect Number of likes
Article tags: Digital IC backend Chip design IC backend implementation Chip design implementation SOC design Analog layout

The picture below shows the Metal Stack used in our community IC back-end training camp project.

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IC backend zero-based introduction Innovus learning tutorial


1P represents one layer of poly, 10M represents 10 layers of metal, M5x represents that M2-M6 is a metal layer with twice the minimum line width, 2
represents that M7-M8 is two The metal layer is eight times the minimum line width. 2z means that M9-M10 is a metal layer eight times the minimum
There is also a layer of AP used to carry RDL. The RDL layer is the thickest and is generally used to connect IO bumps. Signal lines are basically no
using this layer. If it is used for winding, it will not be able to wind a few wires, and it is easy to have DRC problems.

The full English name of RDL is redistribution layer. RDL is a layer of AL on the top metal. Generally speaking, it is a copper process. In the pad are
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bonding, there is also a layer of AL on the top copper for bonding, which is also called an aluminum pad. Aluminum comparison Soft, if there is only

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15/11/2023, 15:57 Digital IC back-end implementation | The difference between TSMC 12nm and TSMC 28nm Metal Stack - C…

bonding cannot be done. Since there is this layer of RDL in the process, it can be used for routing in some designs. It only requires an additional lay
and top metal via mask.

Let’s take another Metal Stack used in the TSMC 12nm project that is about to be opened to the community. From this picture it is clear that there a
and VO. In the previous process, POLY and OD transitioned to Metal1 through Contact. Now there is an additional M0 in the middle. It is worth notin
M2, and M3 in this process are all Double Pattern Layers.

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15/11/2023, 15:57 Digital IC back-end implementation | The difference between TSMC 12nm and TSMC 28nm Metal Stack - C…

The figure below clearly describes the role of M0 and V0 in the physical connection.

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Author: Take this road again Link: https://zhuanlan.zhihu.com/p/25061700 Source: Zhihu copyright belongs to the author. For commercial reprinting, please contact the a

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15/11/2023, 15:57 Digital IC back-end implementation | The difference between TSMC 12nm and TSMC 28nm Metal Stack - C…

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tsmc 28nm process library


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