1. Get the count of Clock buffers?

2. llx lly urx ury all four coordinate of an instance

3. Get all the NDR used in the design
4. Get the routing status of a net
5. Find the name of all the CTS clock nets
6. Find the net name connected to a pin of an instance
7. Find the name of all the nets with a particular pattern in net name
8. Get all the signal nets only (except clock, power and ground)
9. Get the name of all the nets in the design
10. Find the placement status of an instance
11. Get all nets having max fanout greater than specified number
12. Find the width and height of a cell
13. Get the temperature and delay corners of design
14. Get the name of all the instance in your design which has fixed placement
status
15. Find the name of all the don’t touch instance
16. Find the name of all sequential elements (registers/flip flops) in the design
17. Find the name of all the macro’s in your design
18. Find total numbers of well tap instances used in the design
19. Find all the instances which have only one pins (like tie cells, antenna cells)
20. Find the total number of physical cell instances used in the design
21. Get the clock skew and latency reports
22. Get the edge number where a port is placed
23. Get all clock and scan clock pins
24. Get all input and output ports
25. Find the metal layers used in block level IO ports
26. Get all the power domains available in the design
27. Get the area and size of your block
28. Get all the inverter and buffer cells available in the library
29. Get the information of a cell which is present in std. cell library but not in
design.
30. Get the parameters of any particular routing layer (like Masks, Directions,
pitch, min-width, min-spacing etc )
31. Get all the routing layers name
 32. Get all the layers name
33. Get all the pins of a selected Instance.
34. Get the cell name of a selected Instance.
35. Find the top name of the design
36. Get the name of the selected object (instance, net, ports or any other objects).
37. Report the top worst failing 100 late timing paths with the endpoint and slack
values.
38. Report the count of the unique lib cell types of all buffers/inverters in the data
path of a timing path.
39.Find the CPPR value and CPPR branch point of a timing path.
Report the skew between the launch clock and capture clock of a
timing path, considering CPPR.
40. Find the flops receiving no clocks
41. Find the number of logic depth (combinational) in a timing path.
42. Get drivers and receivers (loads) of a net.
43. Query if a net is a clock net.
44. Check if a net is marked as dont_touch
45. Get the library name and base cell name of an instance.
46. Get the maximum transition and maximum capacitance of a pin.
47. Find the clock period of a clock in a particular analysis view.
48. command to check unconnected pins & nets?
49. command to set analysis mode?
50.
51. command to get all signal nets only and whose fanout / pin count > 4 ?
52. Get the count of ULVT cells in the design (excluding physical only cells)