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The architecture was conceived by Cray award winner Monty Denneau, who is currently leading the
project.
[edit]Architecture overview
Each 64-bit Cyclops64 chip (processor) will run at 500 megahertz and contain 80 processors. Each
processor will have two thread units and a floating point unit. A thread unit is an in-order 64-
bit RISC core with 32 kB scratch pad memory, using a 60-instruction subset of the Power
Architecture instruction set. Five processors share a 32 kB instruction cache.
The processors will be connected with a 96 port, 7 stage non-internally blocking crossbar switch. They
will communicate with each other via global interleaved memory (memory that can be written to and
read by all threads) in the SRAM.
[edit]Software
Cyclops64 exposes much of the underyling hardware to the programmer, allowing the programmer to
write very high performance, finely tuned software. One negative consequence is that efficiently
programming Cyclops64 is difficult.[citation needed]
There are around 100 Pthreads procedures, all prefixed "pthread_" and they can be categorized into
four groups:
The POSIX semaphore API works with POSIX threads but is not part of threads standard, having
been defined in the POSIX.1b, Real-time extensions (IEEE Std 1003.1b-1993) standard.
Consequently the semaphore procedures are prefixed by "sem_" instead of "pthread_".
[edit]Example
#define NUM_THREADS 5
return NULL;
}
exit(EXIT_SUCCESS);
}
This program creates five threads, each executing the function TaskCode that prints the unique
number of this thread to standard output.
[edit]See also