Module 2:

CMOS
Transistor
Theory
 Outline
 Lesson 2.1: MOS Devices
– MOS Capacitor
– nMOS IV Characteristics
– pMOS IV Characteristics
– Gate and Diffusion Capacitance
 Lesson 2.2: Non-ideal IV Effects
– Channel Length Modulation
– Body Effect
– Leakage
 Lesson 2.3: DC Characteristics
– Inverter DC Characteristics
– Pass Transistor DC Characteristics
– Noise
CMOS VLSI Design 4th Ed. 2
 Introduction
 So far, we have treated transistors as ideal switches
 An ON transistor passes a finite amount of current
– Depends on terminal voltages
– Derive current-voltage (I-V) relationships
 Transistor gate, source, drain all have capacitance
– I = C (V/t) -> t = (C/I) V
– Capacitance and current determine speed

CMOS VLSI Design 4th Ed. 3

 MOS Capacitor
 Gate and body form MOS
capacitor polysilicon gate
V <0
 Operating modes +
g
silicon dioxide insulator

- p-type body
– Accumulation
– Depletion (a)

– Inversion 0<V <V g t

depletion region
+
-

(b)

Vg > Vt
inversion region
+
- depletion region

(c)

CMOS VLSI Design 4th Ed. 4

 Terminal Voltages
 Mode of operation depends on Vg, Vd, Vs Vg

+ +
– Vgs = Vg – Vs Vgs Vgd
- -
– Vgd = Vg – Vd
Vs Vd
-
– Vds = Vd – Vs = Vgs - Vgd Vds +

 Source and drain are symmetric diffusion terminals

– By convention, source is terminal at lower voltage
– Hence Vds  0
 nMOS body is grounded. First assume source is 0 too.
 Three regions of operation
– Cutoff
– Linear
– Saturation
CMOS VLSI Design 4th Ed. 5
 nMOS Cutoff
 No channel
 Ids ≈ 0

Vgs = 0 Vgd
+ g +
- -
s d
n+ n+

p-type body
b

CMOS VLSI Design 4th Ed. 6

 nMOS Linear
 Channel forms
 Current flows from d to s
V > Vt
– e from s to d Vgd = Vgs
gs
- + g +
- -
 Ids increases with Vds s d
Vds = 0
n+ n+

 Similar to linear resistor p-type body

b

Vgs > Vt
Vgs > Vgd > Vt
+ g +
- - Ids
s d
n+ n+
0 < Vds < Vgs-Vt
p-type body
b

CMOS VLSI Design 4th Ed. 7

 nMOS Saturation
 Channel pinches off
 Ids independent of Vds
 We say current saturates
 Similar to current source

Vgs > Vt
g Vgd < Vt
+ +
- -
s d Ids

n+ n+
Vds > Vgs-Vt
p-type body
b

CMOS VLSI Design 4th Ed. 8

 I-V Characteristics
 In Linear region, Ids depends on
– How much charge is in the channel?
– How fast is the charge moving?

CMOS VLSI Design 4th Ed. 9

 Channel Charge
 MOS structure looks like parallel plate capacitor
while operating in inversions
– Gate – oxide – channel
 Qchannel = CV
 C = Cg = oxWL/tox = CoxWL Cox = ox / tox
 V = Vgc – Vt = (Vgs – Vds/2) – Vt
gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

CMOS VLSI Design 4th Ed. 10

 Carrier velocity
 Charge is carried by e-
 Electrons are propelled by the lateral electric field
between source and drain
– E = Vds/L
 Carrier velocity v proportional to lateral E-field
– v = E  called mobility
 Time for carrier to cross channel:
– t=L/v

CMOS VLSI Design 4th Ed. 11

 nMOS Linear I-V
 Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
Qchannel
I ds 
t
W V  V  Vds V
 Cox  gs t  ds
L 2 
W
  Vgs  Vt  ds Vds
V  = Cox
 2 L

CMOS VLSI Design 4th Ed. 12

 nMOS Saturation I-V
 If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
 Now drain voltage no longer increases current

I ds   Vgs  Vt  dsat V
V
2  dsat
 

  Vt 
2
 Vgs
2

CMOS VLSI Design 4th Ed. 13

 nMOS I-V Summary
 Shockley 1st order transistor models


 0 Vgs  Vt cutoff

  Vds V V  V
I ds    Vgs  Vt   ds linear
 2 
ds dsat

 
Vgs  Vt 
2
 Vds  Vdsat saturation
2

CMOS VLSI Design 4th Ed. 14

 nMOS I-V Summary
 Shockley 1st order transistor models


 0 Vgs  Vt cutoff

  Vds V V  V
I ds    Vgs  Vt   ds linear
 2 
ds dsat

 
Vgs  Vt 
2
 Vds  Vdsat saturation
2

CMOS VLSI Design 4th Ed. 15

 Example
 We will be using a 0.6 m process for your project
– From AMI Semiconductor

2.5
Vgs = 5

1.5 Vgs = 4
Ids (mA)

1
Vgs = 3
0.5
Vgs = 2
Vgs = 1
0
0 1 2 3 4 5
Vds

CMOS VLSI Design 4th Ed. 16

 pMOS I-V
 All dopings and voltages are inverted for pMOS
– Source is the more positive terminal
 Mobility p is determined by holes
– Typically 2-3x lower than that of electrons n
 Thus pMOS must be wider to 0
Vgs = -1

provide same current -0.2

Vgs = -2

Vgs = -3
– In this class, assume

Ids (mA)
-0.4

n / p = 2 Vgs = -4

-0.6

Vgs = -5
-0.8
-5 -4 -3 -2 -1 0
Vds

CMOS VLSI Design 4th Ed. 17

 Capacitance
 Any two conductors separated by an insulator have
capacitance
 Gate to channel capacitor is very important
– Creates channel charge necessary for operation
 Source and drain have capacitance to body
– Across reverse-biased diodes
– Called diffusion capacitance because it is
associated with source/drain diffusion

CMOS VLSI Design 4th Ed. 18

 Gate Capacitance
 Approximate channel as connected to source
 Cgs = oxWL/tox = CoxWL = CpermicronW
 Cpermicron is typically about 2 fF/m

polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.90)
p-type body

CMOS VLSI Design 4th Ed. 19

 Outline
 Lesson 2.1: MOS Devices
– MOS Capacitor
– nMOS IV Characteristics
– pMOS IV Characteristics
– Gate and Diffusion Capacitance
 Lesson 2.2: Non-ideal IV Effects
– Channel Length Modulation
– Body Effect
– Leakage
 Lesson 2.3: DC Characteristics
– Inverter DC Characteristics
– Pass Transistor DC Characteristics
– Noise
CMOS VLSI Design 4th Ed. 20
 Ideal Transistor I-V
 Shockley long-channel transistor models


 0 Vgs  Vt cutoff

  Vds V V  V
I ds    Vgs  Vt   ds linear
 2 
ds dsat

 
Vgs  Vt 
2
 Vds  Vdsat saturation
2

CMOS VLSI Design 4th Ed. 21

Ideal vs. Simulated nMOS I-V Plot
 65 nm IBM process, VDD = 1.0 V
Ids (A)

Simulated
Vgs = 1.0
Ideal
1200
Velocity saturation & Mobility degradation:
Ion lower than ideal model predicts

1000
Ion = 747 mA @
Channel length modulation: V = V = V
gs ds DD
Saturation current increases
800 with Vds Vgs = 1.0

Vgs = 0.8
600
Velocity saturation & Mobility degradation:
Vgs = 0.8
Saturation current increases less than
400 quadratically with Vgs

Vgs = 0.6
200 Vgs = 0.6
Vgs = 0.4
0 Vds
0 0.2 0.4 0.6 0.8 1

CMOS VLSI Design 4th Ed. 22

Channel Length Modulation
 When the channel is pinched off, the length of the
channel is reduced.

VDD VDD
–Leff = L – Ld GND
Source Gate Drain
Depletion Region
 Shorter Leff gives more current Width: Ld

–Ids increases with Vds n L n

+ Leff +
–Even in saturation p GND bulk Si

CMOS VLSI Design 4th Ed. 23

 Chan Length Mod I-V


  Vt  1  Vds 
2
I ds  Vgs
2

  = channel length modulation coefficient

– not feature size
– Empirically fit to I-V characteristics

CMOS VLSI Design 4th Ed. 24

Body Effect

CMOS VLSI Design 4th Ed. 25

 Leakage Sources
 Subthreshold conduction
– Transistors can’t abruptly turn ON
or OFF
– Dominant source in contemporary
transistors
 Gate leakage
– Tunneling through ultrathin gate
dielectric
 Junction leakage
– Reverse-biased PN junction
diode current

4: Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 26

 Subthreshold Leakage
 Subthreshold happens when Vgs<Vt

 Subthreshold leakage exponential with Vgs

Vgs Vt 0 Vds  k Vsb
 Vds

I ds  I ds 0 e nvT
1  e vT 
 
 

 n is process dependent
– typically 1.3-1.7

4: Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 27

 Gate Leakage
 Carriers tunnel thorough very thin gate oxides
 Exponentially sensitive to tox and VDD

– A and B are tech constants

– Greater for electrons
• So nMOS gates leak more
From [Song01]

4: Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 28

 Junction Leakage
 Reverse-biased p-n junctions have some leakage
– Ordinary diode leakage

p+ n+ n+ p+ p+ n+

n well
p substrate

4: Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 29

 Diode Leakage
 Reverse-biased p-n junctions have some leakage
 VvD 
I D  I S  e  1
T

 
 
 At any significant negative diode voltage, ID = -Is
 Is depends on doping levels
– And area and perimeter of diffusion regions

4: Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 30

 Temperature Sensitivity
 Increasing temperature
– Reduces mobility
– Reduces Vt
 ION decreases with temperature
 IOFF increases with temperature

I ds

increasing
temperature

Vgs

4: Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 31

 Parameter Variation
 Transistors have uncertainty in parameters
– Process: Leff, Vt, tox of nMOS and pMOS
– Vary around typical (T) values

fast
 Fast (F) SF
FF

– Leff: short

pMOS
TT

– Vt: low FS
SS
– tox: thin

slow
 Slow (S): opposite slow
nMOS
fast

 Not all parameters are independent

for nMOS and pMOS
4: Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 32
 Environmental Variation
 VDD and T also vary in time and space
 Fast:
– VDD: high
– T: low

Corner Voltage Temperature

F 1.98 0C
T 1.8 70 C
S 1.62 125 C

4: Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 33

 Process Corners
 Process corners describe worst case variations
– If a design works in all corners, it will probably
work for any variation.
 Describe corner with four letters (T, F, S)
– nMOS speed
– pMOS speed
– Voltage
– Temperature

4: Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 34

 Outline
 Lesson 2.1: MOS Devices
– MOS Capacitor
– nMOS IV Characteristics
– pMOS IV Characteristics
– Gate and Diffusion Capacitance
 Lesson 2.2: Non-ideal IV Effects
– Channel Length Modulation
– Body Effect
– Leakage
 Lesson 2.3: DC Characteristics
– Inverter DC Characteristics
– Pass Transistor DC Characteristics
– Noise
CMOS VLSI Design 4th Ed. 35
 DC Response
 DC Response: Vout vs. Vin for a gate
 Ex: Inverter
– When Vin = 0 -> Vout = VDD
– When Vin = VDD -> Vout = 0
VDD
– In between, Vout depends on
Idsp
transistor size and current Vin Vout
– By KCL, must settle such that Idsn
Idsn = |Idsp|
– We could solve equations
– But graphical solution gives more insight
5: DC and Transient Response CMOS VLSI Design 4th Ed. 36
 Transistor Operation
 Current depends on region of transistor behavior
 For what Vin and Vout are nMOS and pMOS in
– Cutoff?
– Linear?
– Saturation?

5: DC and Transient Response CMOS VLSI Design 4th Ed. 37

 nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn
Vout < Vin - Vtn Vout > Vin - Vtn
VDD
Vgsn = Vin Idsp
Vin Vout
Vdsn = Vout Idsn

5: DC and Transient Response CMOS VLSI Design 4th Ed. 38

 pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp
Vout > Vin - Vtp Vout < Vin - Vtp
VDD
Vgsp = Vin - VDD Vtp < 0 Idsp
Vin Vout
Vdsp = Vout - VDD Idsn

5: DC and Transient Response CMOS VLSI Design 4th Ed. 39

 I-V Characteristics
 Make pMOS is wider than nMOS such that n = p
Vgsn5

Idsn Vgsn4

-Vdsp Vgsn3
-VDD Vgsn2
Vgsp1 Vgsn1
Vgsp2 0 VDD
Vgsp3 Vdsn

Vgsp4 -Idsp

Vgsp5

5: DC and Transient Response CMOS VLSI Design 4th Ed. 40

 DC Transfer Curve
 Transcribe points onto Vin vs. Vout plot

Vin0 Vin1
VDD Vin2
Vin0 Vin5
A B

Vout
Vin1 Vin4
C

Vin2 Vin3
Vin3
Vin3 Vin2 D Vin4 Vin5
Vin4 Vin1 E
0 Vtn VDD/2 VDD+Vtp
VDD VDD
Vout Vin

5: DC and Transient Response CMOS VLSI Design 4th Ed. 41

 Operating Regions
 Revisit transistor operating regions VDD

Vin Vout

Region nMOS pMOS

A Cutoff Linear VDD
B Saturation Linear A B

C Saturation Saturation Vout

C
D Linear Saturation
E Linear Cutoff
D
E
0 Vtn VDD/2 VDD+Vtp
VDD
Vin

5: DC and Transient Response CMOS VLSI Design 4th Ed. 42

 Beta Ratio
 If p / n  1, switching point will move from VDD/2
 Called skewed gate
 Other gates: collapse into equivalent inverter
VDD
p
 10
n
Vout 2
1
0.5
p
 0.1
n

0
VDD
Vin

5: DC and Transient Response CMOS VLSI Design 4th Ed. 43

 Transient Response
 DC analysis tells us Vout if Vin is constant
 Transient analysis tells us Vout(t) if Vin(t) changes
– Requires solving differential equations
 Input is usually considered to be a step or ramp
– From 0 to VDD or vice versa

5: DC and Transient Response CMOS VLSI Design 4th Ed. 44

 Inverter Step Response
 Ex: find step response of inverter driving load cap
Vin (t )  u(t  t0 )VDD
Vin(t)
Vout (t  t0 )  VDD Vout(t)
Cload
dVout (t ) I dsn (t )
 Idsn(t)
dt Cload
Vin(t)

 0 t  t0

 
 2
I dsn (t )   2
VDD  V t Vout  VDD  Vt Vout(t)
 t
   VDD  Vt  Vout (t )  V (t ) V  V  V
 out t0
  2 
out DD t

5: DC and Transient Response CMOS VLSI Design 4th Ed. 45

 Pass Transistors
 We have assumed source is grounded
 What if source > 0?
VDD
– e.g. pass transistor passing VDD
VDD
 Vg = VDD
– If Vs > VDD-Vt, Vgs < Vt
– Hence transistor would turn itself off
 nMOS pass transistors pull no higher than VDD-Vtn
– Called a degraded “1”
– Approach degraded value slowly (low Ids)
 pMOS pass transistors pull no lower than Vtp
 Transmission gates are needed to pass both 0 and 1
5: DC and Transient Response CMOS VLSI Design 4th Ed. 46
 Pass Transistor Ckts

VDD VDD VDD

VDD VDD
VDD
Vs = VDD-Vtn VDD-Vtn
VDD-Vtn VDD-Vtn

VDD
VDD-Vtn
Vs = |Vtp|
VDD VDD-2Vtn
VSS

5: DC and Transient Response CMOS VLSI Design 4th Ed. 47

 Noise Margins
 How much noise can a gate input see before it does
not recognize the input?

Output Characteristics Input Characteristics

VDD
Logical High
Output Range VOH Logical High
Input Range
NMH
VIH
Indeterminate
VIL Region
NML
Logical Low
Logical Low VOL Input Range
Output Range
GND

5: DC and Transient Response CMOS VLSI Design 4th Ed. 48

 Logic Levels
 To maximize noise margins, select logic levels at
– unity gain point of DC transfer characteristic

Vout

Unity Gain Points

VDD
Slope = -1
VOH

 p/ n > 1

Vin Vout

VOL
Vin
0
Vtn VIL VIH VDD- VDD
|Vtp|

5: DC and Transient Response CMOS VLSI Design 4th Ed. 49