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설계 포인트가 달라 .

Seong-Ook Jung
PP A sjung@yonsei.ac.kr

뻇쎄邀
VLSI SYSTEM LAB, YONSEI University
School of Electrical & Electronic Engineering

퐤뺍소썡ㆁ ⇒ Performance ↑
function
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But 문제 생김
were
T.im아마 미리
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( CNN은 洌 유지,
2배씩 늘어간다
 Outline
◆ Introduction
◆ Ideal I-V Characteristics
◆ C-V Characteristics
◆ Nonideal I-V Effects
◆ DC Transfer Characteristics
◆ Switch-level RC Delay Models

YONSEI Univ.
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 Introduction
◆ So far, we have treated transistors as ideal switches
.

◆ An ON transistor passes a finite amount of current

⚫ Depends on terminal voltages
⚫ Derive current-voltage (I-V) relationships

◆ Transistor gate, source, drain all have capacitance

⚫ I = C (DV/Dt) →
⚫ Capacitance and current determine speed

YONSEI Univ.
School of EEE 3 CONFIDENTIAL
 MOS Capacitor
◆ Gate and body form MOS capacitor

◆ Operating modes Vg < 0

polysilicon gate
silicon dioxide insulator
+
⚫ Accumulation (Vg  0) - p-type body

⚫ Depletion (0 < Vg < Vt) (a)

⚫ Inversion (Vg  Vt) 0 < V g < Vt

depletion region
+
-

(b)

V g > Vt
inversion region
+
- depletion region

(c)

YONSEI Univ.
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 Terminal Voltages
◆ Mode of operation depends on Vg, Vd, Vs
Vg
⚫ Vgs = Vg – Vs
+ +
⚫ Vgd = Vg – Vd Vgs Vgd
- -
⚫ Vds = Vd – Vs = Vgs – Vgd
Vs Vd
- +
◆ Source and drain are symmetric diffusion terminals Vds

⚫ By convention, source is terminal at lower voltage for NMOS

⚫ Hence Vds  0
◆ nMOS body is grounded. First assume source is 0 too.
◆ Three regions of operation

YONSEI Univ.
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 nMOS Cutoff
◆ No channel (Vgs < 0)

Vgs = 0 Vgd
+ g +
- -
s d

n+ n+

p-type body
b

YONSEI Univ.
School of EEE 6 CONFIDENTIAL
 nMOS Linear
◆ Channel forms (Vgs  Vt)

Vgs > Vt
Vgd = Vgs
+ g +
- -
s d
n+ n+ Vds = 0

p-type body
b

Vgs > Vt
Vgs > Vgd > Vt
+ g +
- - Ids
s d
n+ n+
0 < Vds < Vgs-Vt
p-type body
b

YONSEI Univ.
School of EEE 7 CONFIDENTIAL
 nMOS Saturation
◆ Channel pinches off (Vgs  Vt and Vgd < Vt )

Vgs > Vt
g Vgd < Vt
+ +
- -
s d Ids

n+ n+
Vds > Vgs-Vt
p-type body
b

YONSEI Univ.
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 I-V Characteristics
◆ In linear region, Ids depends on
⚫ How much charge is in the channel?
⚫ How fast is the charge moving?

YONSEI Univ.
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 Channel Charge (Qchannel)
◆ MOS structure looks like parallel plate capacitor while operating
in inversion
⚫ Gate – oxide – channel
◆ Qchannel = CV, where C = Cg = CoxWL
V = Vgc – Vt = (Vgs – Vds / 2) – Vt
= CoxWL{(Vgs – Vds / 2) – Vt}

gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

YONSEI Univ.
School of EEE 10 CONFIDENTIAL
 Time for Charge Moving (t)
◆ Charge is carried by e-
◆ Carrier velocity v proportional to lateral E-field between source
and drain
◆ v = E, E = Vds / L, v = Vds / L

◆ Time for carrier to cross channel:

⚫ t=L/v=

YONSEI Univ.
School of EEE 11 CONFIDENTIAL
 nMOS Linear I-V
◆ Now we know
⚫ How much charge Qchannel is in the channel
❖ Qchannel = CoxWL{(Vgs – Vds / 2) – Vt}
⚫ How much time t each carrier takes to cross
❖ t = L2 / Vds

Ids = Qchannel / t = CoxWL{(Vgs – Vds / 2) – Vt} Vds / L2

=  {(Vgs – Vds / 2) – Vt}Vds, where  = CoxW/L

=  {(Vgs –Vt)Vds – Vds2 / 2}

YONSEI Univ.
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 nMOS Saturation I-V
◆ If Vgd < Vt, channel pinches off near drain
⚫ When Vds > Vdsat = Vgs – Vt

◆ Now drain voltage no longer increases current

Ids =  {(Vgs – Vds / 2) – Vt}Vds  Vds = Vdsat = Vgs – Vt

YONSEI Univ.
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 nMOS I-V Summary
◆ Shockley 1st order transistor models


 0 Vgs  Vt cutoff

  V V V  V
I ds =   Vgs − Vt − ds  ds linear
 2 
ds dsat

 
(Vgs − Vt )
2
 Vds  Vdsat saturation
2

where  = CoxW/L

YONSEI Univ.
School of EEE 14 CONFIDENTIAL
 Capacitance
◆ Any two conductors separated by an insulator have capacitance
◆ Gate to channel capacitor is very important
⚫ Creates channel charge necessary for operation

◆ Source and drain have capacitance to body

⚫ Across reverse-biased diodes
⚫ Called diffusion capacitance because it is associated with source/drain
diffusion

YONSEI Univ.
School of EEE 15 CONFIDENTIAL
Gate & Diffusion Capacitances
◆ Gate capacitance
Cg = CoxWL = (ox/tox) WL
◆ Diffusion capacitance
Cd = Csb,db = ASCjbs + PS  Cjbsw , where AS = WD, PS = W + 2D

polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.90)
p-type body

YONSEI Univ.
School of EEE 16 CONFIDENTIAL
 Diffusion Capacitance
◆ Csb, Cdb
◆ Undesirable, called parasitic capacitance
◆ Capacitance depends on area and perimeter
⚫ Use small diffusion nodes
⚫ Comparable to Cg
for contacted diff
⚫ ½ Cg for uncontacted
⚫ Varies with process

YONSEI Univ.
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Nonideal Transistor Behavior
◆ High Field Effects
⚫ Mobility Degradation
⚫ Velocity Saturation
◆ Channel Length Modulation
◆ Threshold Voltage Effects
⚫ Body Effect
⚫ Drain-Induced Barrier Lowering
⚫ Short Channel Effect
◆ Leakage
⚫ Subthreshold Leakage
⚫ Gate Leakage
⚫ Junction Leakage

YONSEI Univ.
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Ideal vs. Simulated nMOS I-V Plot
◆ 65 nm IBM process, VDD = 1.0 V
Ids (A)

Simulated
Vgs = 1.0
Ideal
1200
Velocity saturation & Mobility degradation:
Ion lower than ideal model predicts

1000
Ion = 747 mA @
Channel length modulation: V = V = V
gs ds DD
Saturation current increases
800 with Vds Vgs = 1.0

Vgs = 0.8
600
Velocity saturation & Mobility degradation:
Vgs = 0.8
Saturation current increases less than
400 quadratically with Vgs

Vgs = 0.6
200 Vgs = 0.6
Vgs = 0.4
0 Vds
0 0.2 0.4 0.6 0.8 1

YONSEI Univ.
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 ON and OFF Current
Ids (A)

◆ Ion = Ids @ Vgs = Vds = VDD

1000
Ion = 747 mA @
Vgs = Vds = VDD

⚫ Saturation 800 Vgs = 1.0

⚫ 747mA 600

Vgs = 0.8

400

Vgs = 0.6
200

Vgs = 0.4

0 Vds
0 0.2 0.4 0.6 0.8 1

◆ Ioff = Ids @ Vgs = 0, Vds = VDD

⚫ Cutoff
⚫ 27nA/mm

YONSEI Univ.
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 Electric Fields Effects
◆ Vertical electric field: Evert =
⚫ Attracts carriers into channel
⚫ Long channel: Qchannel  Evert
◆ Lateral electric field: Elat =
⚫ Accelerates carriers from drain to source
⚫ Long channel: v = Elat

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 Mobility Degradation
◆ High Evert effectively reduces mobility
⚫ Collisions with oxide interface

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 Velocity Saturation
◆ At high Elat, carrier velocity rolls off
⚫ Carriers scatter off atoms in silicon lattice
⚫ Velocity reaches vsat
❖ Electrons: 107 cm/s
❖ Holes: 8 x 106 cm/s
⚫ Better model

YONSEI Univ.
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 Velocity Sat. I-V Effects
◆ Ideal transistor ON current increases with VDD2

◆ Velocity-saturated ON current increases with VDD

◆ Real transistors are partially velocity saturated

⚫ Approximate with a-power law model
⚫ Ids  VDDa
⚫ 1 < a < 2 determined empirically (1.3 for 65nm

YONSEI Univ.
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 Channel Length Modulation
◆ Reverse-biased p-n junctions form a depletion region
⚫ Region between n and p with no carriers
⚫ Width of depletion Ld region grows with reverse bias
⚫ Leff = L – Ld GND VDD VDD
Source Gate Drain
Depletion Region
◆ Shorter Leff gives ______ current Width: Ld

⚫ Ids _________ with Vds

L
n+ n+
⚫ Even in saturation Leff
p GND bulk Si

YONSEI Univ.
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 Channel Length Mod. I-V

( − Vt ) (1 + lVds )
2
I ds = V
gs
2
◆ l = channel length modulation coefficient
⚫ not feature size
⚫ Empirically fit to I-V characteristics

YONSEI Univ.
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 Threshold Voltage Effects
◆ Vt is Vgs for which the channel starts to invert
◆ Ideal models assumed Vt is constant
◆ Really depends (weakly) on almost everything else:
⚫ Body voltage: Body Effect
⚫ Drain voltage: Drain-Induced Barrier Lowering
⚫ Channel length: Short Channel Effect

YONSEI Univ.
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 Body Effect
Vt = Vt 0 + g ( fs + Vsb − fs )
◆ fs = surface potential at threshold
NA
fs = 2vT ln
ni
⚫ Depends on doping level NA
⚫ And intrinsic carrier concentration ni

◆ g = body effect coefficient

tox 2q si N A
g = 2q si N A =
 ox Cox

YONSEI Univ.
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 DIBL
◆ Electric field from drain affects channel
◆ More pronounced in small transistors where the drain is closer to
the channel
◆ Drain-Induced Barrier Lowering
⚫ Drain voltage also affect Vt

Vt = Vt − Vds

YONSEI Univ.
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 Short Channel Effect
◆ In small transistors, source/drain depletion regions extend into the
channel
⚫ Impacts the amount of charge required to invert the channel
⚫ And thus makes Vt a function of channel length
◆ Short channel effect: Vt increases with L
⚫ Some processes exhibit a reverse short channel effect in which Vt decreases
with L

YONSEI Univ.
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 Leakage
◆ What about current in cutoff in ideal MOS ?

◆ Simulated results

◆ What differs?

YONSEI Univ.
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 Leakage Sources
◆ Junction leakage
⚫ Reverse-biased PN junction diode current

◆ Subthreshold conduction
⚫ Transistors can’t abruptly turn ON or OFF

◆ Gate leakage
⚫ Tunneling through ultrathin gate dielectric

YONSEI Univ.
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 Junction Leakage
◆ Reverse-biased p-n junctions have some leakage
⚫ Ordinary diode leakage
 VvD 
I D = I S  e − 1
T
where, Is depends on doping levels, area and
 
  perimeter of diffusion regions

⚫ Band-to-band tunneling (BTBT)

❖ Tunneling across heavily doped p-n junctions
❖ Especially sidewall between drain & channel when halo doping is used to
increase Vt
❖ Increases junction leakage to significant levels

YONSEI Univ.
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 Subthreshold Leakage
◆ Subthreshold leakage exponential with Vgs
Vgs −Vt
 −Vds

I ds = I ds 0e nvT
 1 − e T
v

 

◆ n is process dependent, typically 1.3-1.7

◆ Subtheshold slope ≈ 100 mV/decade @ room temperature

YONSEI Univ.
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 Gate Leakage
◆ Carriers may tunnel thorough very thin gate oxides
◆ Exponentially sensitive to tox and VDD

⚫ A and B are tech constants

⚫ Greater for electrons
❖ So nMOS gates leak more
◆ Negligible for older processes
(tox > 20 Å)
◆ Critically important at 65 nm
and below (tox ≈ 10.5 Å)

YONSEI Univ.
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 Temperature Sensitivity
◆ Increasing temperature
⚫ Reduces mobility
⚫ Reduces Vt

◆ ION ___________ with temperature

◆ IOFF ___________ with temperature

I ds

increasing
temperature

Vgs

YONSEI Univ.
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 Process Corners
(Parameter Variation
◆ Transistors have uncertainty in parameters
⚫ Process: Leff, Vt, tox of nMOS and pMOS
⚫ Vary around typical (T) values
◆ Fast (F)

fast
FF
SF
⚫ Leff: short
⚫ Vt: low

pMOS
TT

⚫ tox: thin
◆ Slow (S): opposite FS

◆ Not all parameters are independent SS

slow
for nMOS and pMOS slow fast
nMOS

YONSEI Univ.
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Voltage & Temperature Corners
(Environmental Variation)
◆ VDD and T also vary in time and space
◆ Fast:
⚫ VDD: high
⚫ T: low (or high)

Corner Voltage Temperature

F 1.98 0 C (or 125C)
T 1.8 70 C
S 1.62 125 C (or 0C)

YONSEI Univ.
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 Important Corners
◆ Some critical simulation corners include
Purpose nMOS pMOS VDD Temp

Cycle time S S S S

Power F F F F

Subthreshold F F F S (Hot
leakage Temp)

YONSEI Univ.
School of EEE 39 CONFIDENTIAL
 Activity
1) If the width of a transistor increases, the current will
increase decrease not change
2) If the length of a transistor increases, the current will
increase decrease not change
3) If the supply voltage of a chip increases, the maximum transistor current will
increase decrease not change
4) If the width of a transistor increases, its gate capacitance will
increase decrease not change
5) If the length of a transistor increases, its gate capacitance will
increase decrease not change
6) If the supply voltage of a chip increases, the gate capacitance of each
transistor will
increase decrease not change

YONSEI Univ.
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 DC Response
◆ Revisit transistor operating regions VDD

Region nMOS pMOS Vin Vout

A
B
C VDD
A B
D
E Vout
C

D
E
0 Vtn VDD/2 VDD+Vtp
VDD
Vin

YONSEI Univ.
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 Beta Ratio
◆ If p / n  1, switching point will move from VDD/2

◆ Other gate can be modeled by an equivalent inverter

VDD
p
= 10
n
Vout 2
1
0.5
p
= 0.1
n

0
VDD
Vin

YONSEI Univ.
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 Noise Margins
◆ How much noise can a gate input see before it does not recognize
the input?

Output Characteristics Input Characteristics

VDD
Logical High
Output Range VOH Logical High
Input Range
VIH
Indeterminate
VIL Region

Logical Low
Logical Low VOL Input Range
Output Range
GND

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 Logic Levels
◆ To maximize noise margins, select logic levels at

Vout

VDD

p/n > 1

Vin Vout

Vin
0
VDD

YONSEI Univ.
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