Lecture 4:

Nonideal
Transistor
Theory
 Outline
 Nonideal Transistor Behavior
– High Field Effects
• Mobility Degradation
• Velocity Saturation
– Channel Length Modulation
– Threshold Voltage Effects
• Body Effect
• Drain-Induced Barrier Lowering
• Short Channel Effect
– Leakage
• Subthreshold Leakage
• Gate Leakage
• Junction Leakage
 Process and Environmental Variations

4: Nonideal Transistor Theory CMOS VLSI Design 3rd Ed. 2

 Ideal Transistor I-V
 Shockley long-channel transistor models


 0 Vgs  Vt cutoff

  Vds V V  V
I ds     Vgs  Vt   ds linear
 2 
ds dsat

 
Vgs  Vt 
2
 Vds  Vdsat saturation
2

4: Nonideal Transistor Theory CMOS VLSI Design 3rd Ed. 3

Ideal vs. Simulated nMOS I-V Plot
 65 nm IBM process, VDD = 1.0 V
Ids (A)

Simulated
Vgs = 1.0
Ideal
1200
Velocity saturation & Mobility degradation:
Ion lower than ideal model predicts

1000
Ion = 747 mA @
Channel length modulation: V = V = V
gs ds DD
Saturation current increases
800 with Vds Vgs = 1.0

Vgs = 0.8
600
Velocity saturation & Mobility degradation:
Vgs = 0.8
Saturation current increases less than
400 quadratically with Vgs

Vgs = 0.6
200 Vgs = 0.6
Vgs = 0.4
0 Vds
0 0.2 0.4 0.6 0.8 1

4: Nonideal Transistor Theory CMOS VLSI Design 3rd Ed. 4

 ON and OFF Current
Ids (A)

 Ion = Ids @ Vgs = Vds = VDD 1000

Ion = 747 mA @
Vgs = Vds = VDD

800 Vgs = 1.0

– Saturation 600

Vgs = 0.8

400

Vgs = 0.6
200

Vgs = 0.4

0 Vds
0 0.2 0.4 0.6 0.8 1

 Ioff = Ids @ Vgs = 0, Vds = VDD

– Cutoff

4: Nonideal Transistor Theory CMOS VLSI Design 3rd Ed. 5

 Electric Fields Effects
 Vertical electric field: Evert = Vgc / tox = (Vgs - Vds /2)/ tox
– Attracts carriers into channel
– Long channel: Qchannel  Evert
 Lateral electric field: Elat = Vds / L
– Accelerates carriers from drain to source
– Long channel: v = Elat

4: Nonideal Transistor Theory CMOS VLSI Design 3rd Ed. 6

 Mobility Degradation
 High Evert effectively reduces mobility
– Collisions with oxide interface

4: Nonideal Transistor Theory CMOS VLSI Design 3rd Ed. 7

 Velocity Saturation
 At high Elat, carrier velocity rolls off
– Carriers scatter off atoms in silicon lattice
– Velocity reaches vsat
• Electrons: 107 cm/s
• Holes: 8 x 106 cm/s
– Better model

4: Nonideal Transistor Theory CMOS VLSI Design 3rd Ed. 8

Channel Length Modulation
 Reverse-biased p-n junctions form a depletion region
– Region between n and p with no carriers
– Width of depletion Ld region grows with reverse bias
GND VDD VDD

– Leff = L – Ld Source Gate Drain

Depletion Region
Width: Ld
 Shorter Leff gives more current
– Ids increases with Vds n
+
L n
+
Leff

– Even in saturation p GND bulk Si

4: Nonideal Transistor Theory CMOS VLSI Design 3rd Ed. 9

 Chan Length Mod I-V


I ds  Vgs  Vt  1  Vds 
2

  = channel length modulation coefficient

– not feature size
– Empirically fit to I-V characteristics

4: Nonideal Transistor Theory CMOS VLSI Design 3rd Ed. 10

 Threshold Voltage Effects
 Vt is Vgs for which the channel starts to invert
 Ideal models assumed Vt is constant
 Really depends (weakly) on almost everything else:
– Body voltage: Body Effect
– Drain voltage: Drain-Induced Barrier Lowering
– Channel length: Short Channel Effect

4: Nonideal Transistor Theory CMOS VLSI Design 3rd Ed. 11

 Body Effect
 Body is a fourth transistor terminal
 Vsb affects the charge required to invert the channel
– Increasing Vs or decreasing Vb increases Vt
Vt  Vt 0    s  Vsb  s 
 s = surface potential at threshold
NA
s  2vT ln
ni

– Depends on doping level NA

– And intrinsic carrier concentration ni
  = body effect coefficient
tox 2q si N A
  2q si N A 
 ox Cox

4: Nonideal Transistor Theory CMOS VLSI Design 3rd Ed. 12

 DIBL
 Electric field from drain affects channel
 More pronounced in small transistors where the
drain is closer to the channel
 Drain-Induced Barrier Lowering
VVV ttds

– Drain voltage also affect Vt

Vt   Vt  Vds
 High drain voltage causes current to increase.

4: Nonideal Transistor Theory CMOS VLSI Design 3rd Ed. 13

 Short Channel Effect
 In small transistors, source/drain depletion regions
extend into the channel
– Impacts the amount of charge required to invert
the channel
– And thus makes Vt a function of channel length
 Short channel effect: Vt increases with L
– Some processes exhibit a reverse short channel
effect in which Vt decreases with L

4: Nonideal Transistor Theory CMOS VLSI Design 3rd Ed. 14

 Leakage
 What about current in cutoff?
 Simulated results
 What differs?
– Current doesn’t
go to 0 in cutoff

4: Nonideal Transistor Theory CMOS VLSI Design 3rd Ed. 15

 Leakage Sources
 Subthreshold conduction
– Transistors can’t abruptly turn ON or OFF
 Gate leakage
– Tunneling through ultrathin gate dielectric
 Junction leakage
– Reverse-biased PN junction diode current

4: Nonideal Transistor Theory CMOS VLSI Design 3rd Ed. 16

 Temperature Sensitivity
 Increasing temperature
– Reduces mobility
– Reduces Vt
 ION decreases with temperature
 IOFF increases with temperature

I ds

increasing
temperature

Vgs

4: Nonideal Transistor Theory CMOS VLSI Design 3rd Ed. 17

 Parameter Variation
 Transistors have uncertainty in parameters
– Process: Leff, Vt, tox of nMOS and pMOS
– Vary around typical (T) values
 Fast (F)

fast
FF
SF

– Leff: short

pMOS
TT

– Vt: low
FS

– tox: thin SS

slow
 Slow (S): opposite slow
nMOS
fast

 Not all parameters are independent

for nMOS and pMOS
4: Nonideal Transistor Theory CMOS VLSI Design 3rd Ed. 18
 Process Corners
 Process corners describe worst case variations
– If a design works in all corners, it will probably
work for any variation.
 Describe corner with four letters (T, F, S)
– nMOS speed
– pMOS speed
– Voltage
– Temperature

4: Nonideal Transistor Theory CMOS VLSI Design 3rd Ed. 19