Logical Effort Anitha

logical effort-Anitha R.
Introduction Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Example Summary
Chip designers face a bewildering array of choices

What is the best circuit topology for a function? How many stages of logic give least delay? How wide should the transistors be?
???
Logical effort is a method to make these decisions

Uses a simple model of delay Allows back-of-the-envelope calculations Helps make rapid comparisons between alternatives Emphasizes remarkable symmetries
Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive processor. Help Ben design the decoder for a register file.
A[33 A[33 : ] : ] 3 bits 3
Decoder specifications:

16 word register file Each word is 32 bits wide Each bit presents load of 3 unit-sized transistors True and complementary address inputs A[3:0] Each input may drive 10 unit-sized transistors
33 Decoder : 3
3 words 3
3 3
Register File
Ben needs to decide:

How many stages to use? How large should each gate be? How fast can decoder operate?
Express delays in process-independent unit
d abs d=
3RC
12 ps in 180 nm process 40 ps in 0.6 m process
Delay has two components
d abs d=
d= f +p
Delay has two components Effort delay f = gh (a.k.a. stage effort)

Again has two components
d abs d=
d= f +p
Delay has two components Effort delay f = gh (a.k.a. stage effort) Again has two components g: logical effort Measures relative ability of gate to deliver current g 1 for inverter
d abs d=
d= f +p
Delay has two components Effort delay f = gh (a.k.a. stage effort) Again has two components h: electrical effort = Cout / Cin Ratio of output to input capacitance Sometimes called fanout
d abs d=
d= f +p
Delay has two components
d abs d=
d= f +p
Parasitic delay p
Represents delay of gate driving no load Set by internal parasitic capacitance
d =f+p = gh + p
NormalizedDelay:d
3 3 3 3 3 3 3 3 3 3
3 -input NAND
Inverter g= p= d=
g= p= d=
ElectricalEffort: h = Cout / Cin
d =f+p = gh + p
NormalizedDelay:d
3 3 3 3 3 3
3 -input NAND
Inverter g = 33 / p=3 d = ( 33 + 3 / )h
What about NOR2?
g=3 p=3 d = h +3 EffortDelay:f
Parasitic Delay: p
3 3 3 3 3 3 3
ElectricalEffort: h = Cout / Cin
DEF: Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current. Measure from delay vs. fanout plots Or estimate by counting transistor widths
3 A 3 Y 3 Cin = 3 g = 33 / A B Cin = 3 g = 33 / 3 3 3 Y A B 3 Cin = 3 g = 33 / 3 3 3 Y
Logical effort of common gates Gate type 1 Inverter NAND NOR Tristate / mux 2 XOR, XNOR 1 4/3 5/3 2 4, 4 5/3 7/3 2 6/3 9/3 2 (n+2)/3 (2n+1)/3 2 2 Number of inputs 3 4 n
6, 12, 6 8, 16, 16, 8

Parasitic delay of common gates In multiples of pinv ( 1)
Gate type 1 Inverter NAND NOR Tristate / mux 2 XOR, XNOR 1 2 2 4 4 2
Number of inputs 3 3 3 6 6 4 4 4 8 8
n n n 2n
Estimate the frequency of an N-stage ring oscillator
Logical Effort: Electrical Effort: Parasitic Delay: Stage Delay: Frequency: fosc =
g h p d
= = = =
Estimate the frequency of an N-stage ring oscillator
Logical Effort: g=1 Electrical Effort: h = 1 Parasitic Delay: p=1 Stage Delay: d=2 Frequency: fosc = 1/(2*N*d) = 1/4N
31 stage ring oscillator in 0.6 m process has frequency of ~ 200 MHz
Estimate the delay of a fanout-of-4 (FO4) inverter

d
Logical Effort: g = Electrical Effort: Parasitic Delay: Stage Delay: d=
h= p=
Estimate the delay of a fanout-of-4 (FO4) inverter

d
Logical Effort: g = 1 Electrical Effort: h = 4 The FO4 delay is about Parasitic Delay: p = 1 200 ps in 0.6 m process Stage Delay: d=5
60 ps in a 180 nm process f/3 ns in an f m process
Logical effort generalizes to multistage networks Path Logical Effort Path Electrical Effort Path Effort
F = f i = gi hi
x g3= 33 / h3= y/x z g3= 3 h3= 33 /z
G = gi Cout-path H= Cin-path
3 3 g3= 3 h3= x/33
y g3= 33 / h3= z/y
3 3
Logical effort generalizes to multistage networks Path Logical Effort G= g
Path Electrical Effort Path Effort Can we write F = GH?
H=
Cout path Cin path
F = f i = gi hi
No! Consider paths that branch:

3 3
G H GH h1 h2 F
= = = = = = GH?
3 3
3 3 3 3 3
No! Consider paths that branch:

3 3
G H GH h1 h2 F
=1 = 90 / 5 = 18 = 18 = (15 +15) / 5 = 6 = 90 / 15 = 6
3 3
3 3 3 3 3
= g1g2h1h2 = 36 = 2GH
Introduce branching effort

Accounts for branching between stages in path
b= B = bi
Con path + Coff path Con path

Note:
i
h Now we compute the path effort

F = GBH
= BH
Path Effort Delay Path Parasitic Delay Path Delay
DF = f i P = pi D = d i = DF + P
D = d i = DF + P
Delay is smallest when each stage bears same effort 3
f = gi hi = F N
Thus minimum delay of N stage path is 3
D = NF N + P
This is a key result of logical effort Find fastest possible delay Doesnt require calculating gate sizes
How wide should the gates be for least delay?
f = gh = g Cout Cin gi Couti Cini = f
Working backward, apply capacitance transformation to find input capacitance of each gate given load it drives. Check work by verifying input cap spec is met.
Select gate sizes x and y for least delay from A to B x

x A 3 x y 3 3 B 3 3
x x A 3 x y 3 3 B 3 3
Logical Effort Electrical Effort Branching Effort Path Effort Best Stage Effort Parasitic Delay Delay
G= H= B= F=
f =
P= D=
x x A 3 x y 3 3 B 3 3
Logical Effort Electrical Effort Branching Effort Path Effort Best Stage Effort Parasitic Delay Delay
G = (4/3)*(5/3)*(5/3) = 100/27 H = 45/8 B=3*2=6 F = GBH = 125
f = 3F = 3
P=2+3+2=7 D = 3*5 + 7 = 22 = 4.4 FO4

Work backward for sizes y= x=

x x A 3 x y 3 3 B 3 3
Work backward for sizes y = 45 * (5/3) / 5 = 15 x = (15*2) * (5/3) / 5 = 10
3 3 A P: 3 N: 3 P: 3 N: 3 P: 33 B 3 3 N: 3
Compare many alternatives with a spreadsheet Design NAND4-INV NAND2-NOR2 INV-NAND4-INV NAND4-INV-INV-INV NAND2-NOR2-INV-INV NAND2-INV-NAND2-INV INV-NAND2-INV-NAND2-INV N 2 2 3 4 4 4 5 G 2 20/9 2 2 20/9 16/9 16/9 16/9 P 5 4 6 7 6 6 7 8 D 29.8 30.1 22.1 21.1 20.5 19.7 20.4 21.6
NAND2-INV-NAND2-INV-INV-INV 6
Term number of stages logical effort electrical effort branching effort effort effort delay parasitic delay delay
Stage
3 g h= b=
Cout Cin Con-path +Coff-path Con-path
Path
N G = gi H=
Cout-path Cin-path
B = bi F = GBH DF = f i P = pi D = d i = DF + P
f = gh f p d= f +p
1) 2) 3) 4) 5)
F = GBH Compute path effort Estimate best number of stages N = log 3F Sketch path with N stages D = NF + P Estimate least delay f =F Determine best stage effort
3 N 3 N
6)
Find gate sizes
gi Couti Cini = f
Dynamic Power Static Power
Power is drawn from a voltage source attached to the VDD pin(s) of a chip.
P Instantaneous Power: (t ) = I (t )V (t )
Energy: Average Power:
E = P (t )dt
3
Pavg
E 3 = = P (t )dt T T 3
P ( t ) = I DD ( t ) VDD VDD
PR ( t ) =
VR3( t ) R
3 = IR ( t ) R
dV EC = I ( t )V ( t ) dt = C V ( t ) dt dt 3 3 = C V ( t ) dV = 3CVC3 3
3
VC
When the gate output rises Energy stored in capacitor is But energy drawn from the supply is
EVDD = I ( t )VDD dt = CL
3 3
3 EC = 3C LVDD 3
dV VDD dt dt
= CLVDD
VDD
dV = C V
3
3 L DD
Half the energy from VDD is dissipated in the pMOS transistor as heat, other half stored in capacitor When the gate output falls Energy in capacitor is dumped to GND Dissipated as heat in the nMOS transistor
Ptotal = Pdynamic + Pstatic
Power Dissipation Sources

Switching load capacitances Short-circuit current
Dynamic power: Pdynamic = Pswitching + Pshortcircuit
Static power: Pstatic = (Isub + Igate + Ijunct + Icontention)VDD

Subthreshold leakage Gate leakage Junction leakage Contention current

Logical Effort Anitha

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logical effort-Anitha R.

Chip designers face a bewildering array of choices

Logical effort is a method to make these decisions

Ben needs to decide:

Express delays in process-independent unit

12 ps in 180 nm process 40 ps in 0.6 m process

Express delays in process-independent unit

Delay has two components

Express delays in process-independent unit

Delay has two components Effort delay f = gh (a.k.a. stage effort)

Express delays in process-independent unit

Express delays in process-independent unit

Express delays in process-independent unit

Delay has two components

ElectricalEffort: h = Cout / Cin

What about NOR2?

g=3 p=3 d = h +3 EffortDelay:f

ElectricalEffort: h = Cout / Cin

6, 12, 6 8, 16, 16, 8

Parasitic delay of common gates In multiples of pinv ( 1)

Gate type 1 Inverter NAND NOR Tristate / mux 2 XOR, XNOR 1 2 2 4 4 2

Estimate the frequency of an N-stage ring oscillator

Estimate the frequency of an N-stage ring oscillator

31 stage ring oscillator in 0.6 m process has frequency of ~ 200 MHz

Estimate the delay of a fanout-of-4 (FO4) inverter

Logical Effort: g = Electrical Effort: Parasitic Delay: Stage Delay: d=

Estimate the delay of a fanout-of-4 (FO4) inverter

3 3 g3= 3 h3= x/33

y g3= 33 / h3= z/y

Logical effort generalizes to multistage networks Path Logical Effort G= g

Path Electrical Effort Path Effort Can we write F = GH?

Cout path Cin path

No! Consider paths that branch:

No! Consider paths that branch:

Introduce branching effort

Con path + Coff path Con path

h Now we compute the path effort

Path Effort Delay Path Parasitic Delay Path Delay

Delay is smallest when each stage bears same effort 3

Thus minimum delay of N stage path is 3

How wide should the gates be for least delay?

f = gh = g Cout Cin gi Couti Cini = f

Select gate sizes x and y for least delay from A to B x

G = (4/3)*(5/3)*(5/3) = 100/27 H = 45/8 B=3*2=6 F = GBH = 125

P=2+3+2=7 D = 3*5 + 7 = 22 = 4.4 FO4

Work backward for sizes y= x=

Work backward for sizes y = 45 * (5/3) / 5 = 15 x = (15*2) * (5/3) / 5 = 10

Find gate sizes

Dynamic Power Static Power

Energy: Average Power:

Ptotal = Pdynamic + Pstatic

Power Dissipation Sources

Dynamic power: Pdynamic = Pswitching + Pshortcircuit

Static power: Pstatic = (Isub + Igate + Ijunct + Icontention)VDD

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G = (4/3)(5/3)(5/3) = 100/27 H = 45/8 B=3*2=6 F = GBH = 125

Work backward for sizes y = 45 * (5/3) / 5 = 15 x = (152) (5/3) / 5 = 10