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18 January 2021 1442 جمادى الثانية5
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Digital IC Design
Lecture 11
Logical Effort of Paths
❑ Decoder specifications:
▪ 16 word register file
▪ Each word is 32 bits wide
▪ Each bit presents load of 3 unit-sized transistors
A[3:0] A[3:0]
▪ True and complementary address inputs A[3:0] 32 bits
4:16 Decoder
❑ Ben needs to decide:
16 words
16
Register File
▪ How many stages to use?
▪ How large should each gate be?
▪ How fast can decoder operate?
10
x z
y
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z
10
x z
y
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z
G =1
H = 90 / 5 = 18 15
90
GH = 18 5
h1 = (15 +15) / 5 = 6
15
h2 = 90 / 15 = 6 90
F = g1g2h1h2 = 36 = 2GH
G =1
H = 90 / 5 = 18 15
90
GH = 18 5
h1 = (15 +15) / 5 = 6
15
h2 = 90 / 15 = 6 90
F = g1g2h1h2 = 36 = 2GH
❑ Note that:
h i = BH
11: Logical Effort for Paths 9
Multistage Delays
❑ Path Effort Delay: We need both gate type 𝑔 and sizing ℎ
DF = f i
❑ Path Parasitic Delay: We need type only (𝑝). Sizing not required.
P = pi
❑ Path Delay: Can we calculate path delay without sizing info?
D = d i = DF + P
▪ YES! ➔ Logical effort method can tell us min delay of a path!
▪ We can use min delay to calculate sizing!
10
x z
y
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z
❑ Mathematics tell us: If product of 𝑓𝑖 is constant, then we can minimize sum of 𝑓𝑖 by making
all 𝑓𝑖 equal! → 𝑓𝑖 = 𝑓መ
10
x z
y
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z
11: Logical Effort for Paths 11
Designing Fast Circuits
DF = f i P = pi D = d i = DF + P
መ
❑ Delay is smallest when each stage bears same effort (𝑓𝑖 = 𝑓)
𝐹 = Π𝑓𝑖 = 𝑓መ 𝑁
𝟏
𝒇 = 𝑭𝑵
❑ Thus minimum delay of N stage path is
1
D = NF + PN
gi Couti
Cini =
fˆ
❑ Working backward, apply capacitance transformation to find input capacitance of each
gate given load it drives.
❑ Check work by verifying input cap spec is met.
y
x
45
A 8
x
y B
45
y
x
45
A 8
x
y B
45
y
x
45
A 8
x
y B
45
y
x
45
A 8
x
y B
45
y
x
45
A 8
x
y B
45
y
x
45
A 8
x
y B
45
❑ x = 10
❑ y = 15
45
A P: 4
P: 4
N: 4 P: 12 B
N: 6 45
N: 3
23
64 64 64 64
D = NF1/N + P = N(64)1/N + N 16 8
23
Datapath Load 64 64 64 64
N: 1 2 3 4
f: 64 8 4 2.8
D: 65 18 15 15.3
Fastest
D = NF1/N + P = N(64)1/N + N 16 8
i =1
D 1 1 1
= − F ln F + F + pinv = 0
N N N
N
pinv + (1 − ln ) = 0
pinv + (1 − ln ) = 0
❑ No closed-form solution for 𝜌 = 𝑓መ
D(N) /D(N)
1.4
1.26
1.2 1.15
1.0
(=6) ( =2.4)
0.0
0.5 0.7 1.0 1.4 2.0
N/ N
❑ 2.4 < < 6 gives delay within 15% of optimal
▪ We can be sloppy!
▪ Designers like = 4 (FO4 ☺)
11: Logical Effort for Paths 26
Example, Revisited
❑ Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive
processor. Help Ben design the decoder for a register file.
❑ Decoder specifications:
▪ 16 word register file
▪ Each word is 32 bits wide
▪ Each bit presents load of 3 unit-sized transistors
A[3:0] A[3:0]
▪ True and complementary address inputs A[3:0] 32 bits
4:16 Decoder
❑ Ben needs to decide:
16 words
16
Register File
▪ How many stages to use?
▪ How large should each gate be?
▪ How fast can decoder operate?
Design N G P D 𝒇𝒐𝒑𝒕
NOR4
NAND4-INV
NAND2-NOR2
INV-NAND4-INV
NAND4-INV-INV-INV
NAND2-NOR2-INV-INV
NAND2-INV-NAND2-INV
INV-NAND2-INV-NAND2-INV
NAND2-INV-NAND2-INV-INV-INV
Design N G P D 𝒇𝒐𝒑𝒕
NOR4 1 3 4 234 230.40
NAND4-INV 2 2 5 29.8 12.39
NAND2-NOR2 2 20/9 4 30.1 13.06
INV-NAND4-INV 3 2 6 22.1 5.36
NAND4-INV-INV-INV 4 2 7 21.1 3.52
NAND2-NOR2-INV-INV 4 20/9 6 20.5 3.61
NAND2-INV-NAND2-INV 4 16/9 6 19.7 3.42
INV-NAND2-INV-NAND2-INV 5 16/9 7 20.4 2.67
NAND2-INV-NAND2-INV-INV-INV 6 16/9 8 21.6 2.27