CSCE 932, Spring 2009

Test Generation for Combinational Logic

1
 Outline
Fundamental Concepts
Structure vs. Function
Boolean Difference
Test Generation Algorithms
Multi-valued Algebras
Complexity of test generation
PODEM
Boolean-Satisfiability Based
Summary

2
 Origins of Stuck-Faults
Eldred (1959) – First use of structural testing
for the Honeywell Datamatic 1000 computer
Galey, Norby, Roth (1961) – First publication of
stuck-at-0 and stuck-at-1 faults
Seshu & Freeman (1962) – Use of stuck-faults
for parallel fault simulation
Poage (1963) – Theoretical analysis of stuck-at
faults

3
Functional vs. Structural ATPG

4
Carry Circuit

5
Functional vs. Structural (Contd)
Functional ATPG – exhaustive set of tests for 129
inputs, 65 outputs:
2129 = 680,564,733,841,876,926,926,749,
214,863,536,422,912 patterns
Using 1 GHz ATE, would take 2.15 x 1022 years
Structural test:
No redundant adder hardware, 64 bit slices
Each with 27 faults (using fault equivalence)
At most 64 x 27 = 1728 faults (tests)
Takes 0.000001728 s on 1 GHz ATE
Designer gives small set of functional tests – augment
with structural tests to boost coverage to 98+ %

6
 Boolean Difference
I will illustrate the concepts in class,
along with illustrative examples.

7
 Multi-valued Algebras
Symbol Meaning Good Failing
M/c M/c
D 1/0 1 0
D 0/1 0 1 Roth’s
0 0/0 0 0 Algebra
1 1/1 1 1
X X/X X X
G0 0/X 0 X
G1 1/X 1 X Muth’s
F0 X/0 X 0 Additions
F1 X/1 X 1

8
 Roth’s and Muth’s Higher-
Order Algebras
Simultaneously represent two machines:
Good circuit machine (1st value)
Bad circuit machine (2nd value)
Better to represent both in the algebra:
Need only 1 pass of ATPG to solve both
Good machine values that preclude bad machine values
become obvious sooner & vice versa
Needed for complete ATPG:
Combinational: Multi-path sensitization, Roth Algebra
Sequential: Muth Algebra -- good and bad machines may
have different initial values due to fault

9
 Path Sensitization Method
Circuit Example
Fault Sensitization
Fault Propagation
Line Justification

10
 Path Sensitization Method
Circuit Example
Try path f – h – k – L blocked at j,
since there is no way to justify the 1 on
i
1 D

D D
1 D
D 0
1

11
 Path Sensitization Method
Circuit Example
Try simultaneous paths f – h – k – L and
g – i – j – k – L blocked at k because
D-frontier (chain of D or D) disappears
1 D
D
1 1
D D
D
1

12
 Path Sensitization Method
Circuit Example
Final try: path g – i – j – k – L – test
found!

0
0 D
1 D
D D D
1
1

13
Complexity of Test Generation
The primary source of complexity is that
the number of sensitizable paths grow
exponentially with the circuit size and in
the worst case the algorithm may have to
search all of them for a solution.

14
Algorithmic Complexity of Test Generation

Algorithmic complexity refers to the worst-

case-time behavior in terms of problem
parameter(s)
For combinational test generation, circuit size
(in number of lines) is used as the parameter.
Sahni and Ibarra* showed NP-completeness
of test generation by reducing a well NP-
complete problem (3-SAT) to the
combinational test-generation problem.

O.H. Ibarra and S. K. Sahni, “Polynomially Complete Fault Detection Problems,” IEEE Trans.
Computers, March 1975, pp.242-249/ 15
PODEM Test Generation Algorithm

Structure-based and fault oriented

Signal values are explicitly assigned at the PIs only;
other values are computed by implication
Eliminates D-algorithm’s need to justify internal signals
Backtracks at PIs only when a contradiction occurs
Many extensions exist with more complex heuristics,
e.g. the FAN algorithm

16
 PODEM Decision Tree

B=1
~

D=0 D=1
~ Unused assignments

 X Back up, no test possible

A=0 A=1
C=1 ~
X No remaining choices
X  
A=1 A=0

X Success, Halt

17
 PODEM Algorithm
Initialize all signal values to unknown
Branch
Repeat
Imply
If(fault is detected) then exit loop
if(no test possible with current ass’t) then
exit Bound else Branch
Forever

18
 PODEM Example

SA0 Fault
x1 =1 &
& z1
x2 &
=1
=1

x3 &
x4 &
& z2
x5 =1

Assume sequential input selection, applying 1 before 0

19
 PODEM Example
SA0 Fault
0 D
x1 = 1 =1 &
& z1
x2 &
=1
=1

x3 &
x4 &
& z2
x5 =1

Step 1: Set x1 = 1 and imply

20
 PODEM Example

SA0 Fault
0 D
x1 = 1 =1 &
& z1
X2 = 1 &
=1
=1

x3 &
x4 &
& z2
=1
x5

Step 2: Set x2 = 1 and imply

21
 PODEM Example

SA0 Fault
0 D
x1 = 1 =1 &
& 1
z1
X2 = 1 0 &
=1
=1
0
x3 = 1 & 1
x4 &
& z2
=1
x5

Step 3: Set x3 = 1 and imply. Fault cannot be detected at

z1 but detection at z2 is still possible.

22
 PODEM Example

SA0 Fault
0 D
x1 = 1 =1 & 1
& 1
z1
X2 = 1 0 &
0 =1
=1
0
x3 = 1 & 1
x4 = 1 & 1
& z2
=1
x5 0

Step 4: Set x4 = 1 and imply. Now the fault cannot be

detected at either output hence need to backtrack.

23
 PODEM Example

SA0 Fault
0 D
x1 = 1 =1 & 1
& 1
z1
X2 = 1 0 &
0 =1
=1
0
x3 = 1 & 1
x4 = 1 & 1
& z2
=1
x5 0

Step 4: Set x4 = 1 and imply. Now the fault cannot be

detected at either output hence need to backtrack.

24
 PODEM Example

SA0 Fault
0 D
x1 = 1 =1 & D’
& 1
z1
X2 = 1 0 &
1 =1
=1
0
x3 = 1 & 1
x4 = 0 & D’
& z2
=1
x5 D’ D

Step 5 (backtrack): Set x4 = 0 and imply. Now the

fault is detected at output z2.

25
 Podem Heuristics
Several heuristics are used for speedup
Line objectives
Selecting alternatives in back-tracing
Selecting alternatives for extending D-path to
an observable output
Many heuristics are based on the
controllability and absorbability estimates
for lines in the circuit

26
 Boolean Satisfiability
Given a Boolean formula in CNF (product-
of-sums), determine if there is an
assignment of variable values that
satisfies the formula.
Special Cases:
2-SAT: CNF clauses have at most 2 literals
3-SAT: CNF clauses have at most 3 literals

27
 Test Generation as a Boolean
Satisfiability Problem
1. Gate Representation (AND Gate Example):
Express C = AB in conjunctive normal form (CNF). The formula is
true iff the values of A, B, and C are consistent with the AND
function.
2. Circuit Representation: Logically AND the CNF for each gate. The
resulting formula, in CNF, is true all the signal values are consistent.
3. Construct the Boolean difference circuit for the target fault (next
slide).
4. Represent the Boolean difference circuit by its CNF formula and set
the signal at its output to 1. An input assignment is a test iff it
satisfies the CNF.

28
The Boolean Difference Circuit

Circuit Under
Test (CUT)

CUT with
Target Fault
Inserted

Set F=1 in the circuit CNF. Any satisfying solution to the resulting formula must be a test for the fault.

29
 Example
A
E
g2 D g3 G
B C1 g5
C g4 F
For line F sa-1 set F=0, F*=1, and H=1.
g1 H
C2
g6 Then the resulting formula is satisfied
D
A by ABC = 0X0 and X01 which are the
g3 E
C1 g2 F* g5* G*
two tests for the fault.
B
C g4 F
g1
C2

g1 g2 g3 g4 g5 g5* g6
C’+C1 C1+D A’+D’+E B’+c2’+F E’+G E’+G* G+G*’+H
C+C1’ C1’+D’ A+E’ B+F’ F’+G F*’+G* G’+G*+H
C’+C2 D+E’ C2+F’ E+F+G’ E+F*+G*’ G+G*+H’
C+C2” G’+G*’+H’

30
 SAT Solvers
The DPLL Algorithm: Davis-Putnam [JACM 7(1) 1960],
and Davis-Putnam-Longemann-Loveland [CACM May
1962]
The line justification step in PODEM [Goel, IEEE TC,
March 1981] can also be used as a SAT solver
The DPLL algorithm has been enhanced in chaff
[Moskewicz et al. DAC 2001] and implemented in mchaff
and zchaff, the latter being the most widely known and
used.
Other SAT solvers to note:
GRASP [Marques-Silva and Sakalla, IEEE TC, May 1999], SATO
[Zhang, Int. Conf. Automated Deduction, 1997]
Generally, the DPLL enhancements try to improve on the
original backtrack algorithm through careful engineering
of all aspects of the search

31
Basic Davis-Putnam (DP)
Backtrack Search for SAT

decide() selects an
unassigned variable and
gives it a value.
bcp() identifies any
variable assignments
required by the current
variable state to satisfy f.
resolveConflict() undoes
implied assignment and
backtracks to try the next
variable assignment

32
 2-SAT Based SAT Solving
The boolean satisfiability problem for
binary clauses (2-SAT) is polynomially
solvable while 3-SAT and the general
satisfiability problem is NP-complete.
This suggests another heuristic of solving
the satisfiability problem: generate and
test solutions for the binary clauses
against the whole CNF until success.

33
Analyzing 2-SAT Constraints Graphically
Step 1 (Construct the implication graph): For each
binary clause (A+B) create the subgraph:

A B

B’ A’

Step 2: Find the transitive closure graph (TC) of the

implication graph.
A B D E
A B D E

C
C

34
 Analyzing 2-SAT Constraints Graphically
Step 3 (Analyze the transitive-closure graph):
(Contradiction): Both (C’,C) and (C,C’) are in the TC. This implies C must be true and false at the same time. This would occur if the fault was redundant (untestable).
(Fixed Signal Values): Only one of (C’,C) and (C,C’) is in the TC this implies C has a fixed binary value.
(Identical Signal Values): If both (A’,B) and (A,B’) are in the TC then literals A and B must assume identical signal values.
(Excluded Signal Value): If (A’,B) is in the TC and no other edges occur between these four literals, then the combination AB=10 is excluded from the solution.

35
 Transitive Closure Test Generation Algorithm (TRAN)*

In TRAN test generation is carried out

entirely by dynamically updating the TC
after each variable assignment and
analyzing it.

*
See, Chakradhar et al. IEEE TCAD, June 1993 and Larrabee, TCAD, January
1992.

36
 TRAN Flow Chart
Circuit with
Fault Y Redundant
Contradiction? Fault
Transitive N
Closure
N Y Both values
Unassigned
Contradiction? tried?
N Variables? N
Y
Y
Assign value Assign next value Unassigned
to a variable to a variable Variables?

Transitive
Test Found Closure Redundant
Fault

37
 History of Algorithm Speedups
Algorithm Est. speedup Year
D-ALG 1 1966
PODEM 7 1981
FAN 23 1983
TOPS 292 1987
SOCRATES 1574 1988
Waicukauski et al. 2189 1990
EST 8765 1991
TRAN 3005 1993
Recursive Learning 485 1995
Tafertshofer et al. 25057 1997

Part of Automatic Test Pattern Generation (ATPG) System

38
Test Generation for
Sequential-Circuits

40
 Time-Frame Expansion
COMB
LOGIC
C

Iterative Logic Array (ILA) Representation

COMB COMB COMB

LOGIC LOGIC LOGIC
Initial Final
C M C M C M
State State
Clock Cycle 0 Clock Cycle 1 Clock Cycle 2

41
Time-Frame Expansion Based Test Generation

-M -2 -1 0 1 0 N

Time Frames for State Time Frames for Fault

Justification Excitation and Propagation
Single Observation:
This approach guarantees that by observing the primary
outputs at the final time frame, the fault will be detected.
The sequential test generation problem is reduced to
combinational test generation but for multiple time
frames and multiple fault instances.

42
 Test Generation Example: 5 valued logic

Conflict
SA0 1 1 D
1 0
x x
1
1 & SA0 1 &
D
=1 1 =1 z0
 z 
D D
0 1 0
1 1 & & 0 0 & &
x Y 1 x
2
1
2
1 Y0
y
y0
Time frame -1 Time frame 0

43
 Test Generation Example: 9 valued logic

SA0 SA0 1/0

1 0 0/1
x x
1
1
1/x & &
=1 z 1 =1 1/x z0
 
0/x
0/x 1/0
0/x 1/1
1 1/x & &
1/x 0 & &
x Y 1 x
2
1
2
1/x Y0
y
y0
Time frame -1 Time frame 0

44
 The “Reset Problem”
Synchronizing sequence is a generalized reset
for FSMs. It reduces the total uncertainty of
the initial state to a known fixed state.
However, the reduction in ambiguity for some
FSMs may not be fast enough to find the
synchronizing sequence by algorithmic means
using 3-valued logic.
Consider the example machine (from Miczo’s
text, p. 273) on the next page

45
Miczo’s Example Machine
Input x: It can be verified that (0,1,0,1,0)
0 1
is the shortest synchronizing sequence
S0 S1 S1
Consider, encoding the states using two
S1 S3 S2 FFs. What is the state ambiguity after
S2 S1 S3 the first 0?
S3 S0 S0
What does it say about the complexity
of sequential ATPG using 3-value
algebra?

46
 0,1,2,3

0,1,3 0,1,2,3
It can be verified (see the
chart on the left) that
0,1,3 0,1,2
(0,1,0,1,0) is the shortest
synchronizing sequence
1,3 1,2,3
Consider, encoding the
states using two FFs.
0,3 0,2
What is the state
ambiguity after the first 0?
1 1,3
0,1 What does it say about
1,2
the complexity of
1,3 sequential ATPG using 3-
1,3 2,3 value algebra?

0,2 0,3

47
Multiple Observation Times*
Some faults may only be testable by observing
outputs at multiple time frames during the
application of the test sequence. Consider the
following example from the paper:
• Verify that the machine has
Input x: no reset sequence.
0 1 • If the initial state is unknown
the output can be either 0 or 1 in
A B,0 C,0 every timeframe.
B C/B,0 B,1 • Hence, single observation time
does not work.
C D/A,1 A,1
Note: The fault shown is functional affecting
D A,1 D,0 state transitions for 0-input in states B and C,
as shown.

* Pomeranz and Reddy, IEEE TC, May 1992

48
Observation Times for Test Sequence (0000)
Time Units for Observation No single observation
Pair 1 2 3 4 time covers all the
pairs
A/A + +
A/B + +
However, if machine
A/C + + +
outputs are observed
A/D + + +
at both time units 2
and 4, all pairs are
B/A + +
covered.
B/B + +
B/C + + + Hence, independent of
B/D + + + the starting state, the
C/A + + fault can be detected
C/B + + only if at least two
C/C + observations are
C/D + made.
D/A + +
D/B + +
D/C +
D/D +

49
 Distinguishing Sequence
in Finite State Machine

Assume two copies of the same FSM,

one starts in state s and the other in
state t. Common inputs to both.
A distinguishing sequence for states s
and t is any input sequence that
produces a different output.

50
 Example
0/0
0/0 What is the shortest distinguishing
sequence for states C and D?
A 1/1 B

1/0 1/1

D C
1/1
0/1
0/1

51
Product Machine
Product
Machine
M1
Common inputs
Product number of
states
STG derived from
M2 component STGs
Represents behavior of
concurrent operation of
M1 and M2.

52
Test as a Distinguishing Sequence of a
Product Machine

Assume the good and

Good faulty machines start in
Machine state s and t
!= The test is any
distinguishing of the
Faulty product machine
Machine
If the good and faulty
machines do not have a
reset state, it may not be
Product possible to find a test with
Machine single observation.

53
 Sequential Circuit ATPG
Simulation-Based Methods
Contrast with target-fault-based:
Main loop starts with an initial sequence of test
vectors (could be random or otherwise)
The sequence is progressively modified and
augmented based on simulation based
evaluation of the testability of the current set,
until the desired level of coverage is reached.
IBM’s SOFTG* is an early example of this
approach.

* T. J. Snethen, “Simulator-Oriented Fault Test Generator,” Proc. DAC, 1977, pp. 88-93.
54
 Other Simulation-Based Methods

Contest
Directed search
Cost functions
Genetic Algorithms
Spectral Methods
Summary

55
 Fault-Simulation Based Test Generation*

Vector source:
Generate Functional (test-bench),
new trial Heuristic (walking 1, etc.),
vectors Weighted random,
random
No
Trial vectors
Stopping
Yes criteria (fault Fault Fault
coverage, CPU
simulator list
time limit, etc.)
satisfied? Restore
Update
circuit
fault
state
list
New faults Yes Test
Stop No
detected? Append vectors
vectors

* See, Agrawal, et al., IEEE-TCAD, 1989

56
 Sequential ATPG Summary
Combinational ATPG algorithms are extended:
Time-frame expansion unrolls time as combinational array
Justification via backward time
Nine-valued logic system
Unlike combinational ATPG:
Completeness not guaranteed using 3-valued logic simulation
Some circuits may require 9-valued D-algebra 5-valued is not enough
Simulation-based ATPG may be a more attractive alternative
Cycle-free circuits (where sequential elements don’t form a cycle
through combinational logic) are much easier to test than cyclic
circuits
Require at most dseq time-frames
Always initializable
DFT a must for large circuits: Either full or partial scan.

61