Logic Gates Objective & Numerical Ans Type Questions : Qa Q2 Q3 Q4 as The Boolean function Y = AB + CD is to be realized using only 2-input NAND gates. The minimum number of gates required is Which one of the following is the correct output (f) of the below circuit ? b “ (A)(a+b)(c+d ) BH (a+o\(c+a) C(a+b)(e+d) (D)(a+b)(a+a) The Boolean expression Y(A, B, C) = A + BC is to be realized using 2-input gates of only one type. What is the minimum number of gates required for the realization ‘The minimum number of 2-input NAND gates required to implement the Boolean function Z= ABC, assuming that A, B and Care available is [GATE 1998, IIT Delhi] (A)iwo (B) three (five (D)six In the figure shown, the output Y is required to be ¥ = AB+CD. The gates G, and G, must be, [GATE 2015, IT Kanpur] Q6 Q7 s— Po G s—Do— my. c D: (A)NOR, OR (B)OR, NAND (C)NAND, OR A EX-OR a AND bi EXNOR (D)AND, NAND For the logic circuit shown in the above figure, what is the required input condition (A,B, C) to make output X = 1? (AL, 0,1 (B)0,0,1 OLLI (D)0, 1,1 Match the logic gates in Column A with their equivalents in Column B. IGATE 2010, IIT Guwahat Column A Column B “=> *=p- —D- *=>- *3D- *=D- “SD “=D-Digital Electronics Codes: P QRS (2 4.13 (B42 13 (2 43.1 (D4 23 1 Q8 Which one of the following expressions Qo Quo does NOT represent exclusive NOR of x and y? [GATE 2013, IIT Bombay] (Ayxy+ xy? (B) x@y (C)x'@y (D)x'ey For the output #* to be | in the logic circuit shown, the input combination should be IGATE 2010, IT Guwahati] sD c (AA (B)A=1,B=0,C=0 (C)A=0,B=1,C=0 (D)A=0, B A, B, C and D are input bits and Y is the output bit in the XOR gate circuit of the figure below. Which of the following statements about the sum Sof A, B,C, D and Yis correct? [GATE 2007, IT Kanpur] 2 > . ae (A)S is always either zero or odd. (B)S is always either zero or even. (C)S= 1 only if the sum of A, B, C and D is (D)S odd, only if the sum of A, B, Cand D is Qu x Qu2 Qu3 Qu4 If the input to the digital circuit consisting of a cascade of 20 X-OR gates is X, then the output ¥ is equal to [GATE 2002, IISc Bangalore] (Ajo (B)I Ox (D)X Letx,@x,@x,@x,=0 where x35. x, are Boolean variables, and @is the XOR operator, Which one of the following must always be TRUE? [GATE 2016, IISc Bangalore] A) yxy xxy=0 (B) x.y +m, (Re (D) x, 4a +a, +x, =0 A bulb in a staircase has two switches, one switch being at the ground floor and the other one at the first floor. The bulb can be turned ON and also can be turned OFF by any one of the switches irrespective of the state of the other switch, The logic of switching of the bulb resembles IGATE 2013, IIT Bombay] (A)an AND gate (B) an OR gate (C)an XOR gate (D) a NAND gate Two square wave of equal period T, but with a time delay + are applied to a digital circuit whose truth table is shown in the following figure. r y ieaees3 Logic Gates Truth table shown below, Q.15 Assume that only x and y logic input are X | YY] Output available, and their complements X and F are not available. What is the minimum number of 2-input NAND gates required to implement x®y? Q.16 In the given figure, the LED [GATE 2001, IIT Kanpur] Koa SV ofo o7/al 1] 0 | a1 =| of of = The high and the low levels of the output of the digital circuit are 5 V and 0 V, respectively. Which one of the following figures shows the correct variation of the average value of the output voltage of ¢ for 0<1<(I'/2)? [GATE 2007, IIT Kanpur LED 1k (A)Emits light when both 5, and S, are closed (B)Emits light when both S, and S, are opened (C) Emits light when S, is opened and S, ¥, closed. (D)Doesn’t emit light, irrespective of the sv switch positions. Q.17 All the logic gates shown in the figure have a propagation delay of 20 ns. Let A=C 72 and B=1 unit time ¢=0. At ¢=0, all the © inputs flip (ie, A=C=1 and B=0) and remain in that state. For ¢>0, output Z=1 for a duration (in ns) of sv [GATE 2015, IIT Kanpur TI? ———— (D) Q.18 Consider the following circuit composed of XOR gates as non — inverting buffers. The non- inverting buffers have delays + 3,=2 ns and 3,=4 ns as shown in the * 25V4 figure. Both XOR gates and all wires haveDigital Electronics 4 zero delay. Assume that all gate inputs, pico-sec, What is the fundamental frequency outputs and wires are stable at logic level 0 of the oscillator output? at time 0. If the following waveform is [GATE 2001, IIT Kanpur] applied at input A, how many transition(s) (change of logic levels) occur(s) at B during the interval from 0 to 10 ns? IGATE 2003, IIT Madras] % ei (A)10 MHz. (B) 100 MHz, : (C1 GHz (D)2 GHz eee ee eae Q.21 The inverters in the ring oscillator circuit Timed 12.3 4 5 6 7 8 910nsiIns shown below are identical. If the output @. (B)2 waveform has a frequency of 10 MHz, the ©3 (D4 propagation delay of each inverter is Q.19 The gates G, and G, in figure have eee Bangalore] propagation delays of 10 nsec and 20 nsec respectively. If the input V; makes an abrupt poo ooo change from logic 0 to 1 at time ¢=4,, then the output waveform /, is (A)Sns (B) 10ns IGATE 2002, IISc Bangalore] (C)20 ns (D) 50 ns Q.1 Consider the logic circuit with input signal TEST shown in the figure. All gates in the figure shown have identical non-zero delay. The signal TEST which was at logic LOW is Z(t, =f, +10nsec,t, =f, +20 nsec, 1, =1, + 30nsec) switched to logic HIGH. The output wi —_ TEST D oureur a — th (A) Stays HIGH throughout @1 (B) Stays LOW throughout (©) Pulses from LOW to HIGH to LOW (D)Pulses from HIGH to LOW to HIGH Or Q.2__ For the circuit shown below the output F is given by 0 0 af OW Q.20. For the ring oscillator shown in the figure, (A)F=1 (B)F=0 the propagation delay of each inverter is 100 (OF=X (D) F=XLogic Gates Q3 Q4 Q5 Q6 Minimum number of 2-input NAND gates required to implement the function, F = (Y +F)(Z+Mis (A)3 (B)4 (os (D)6 Indicate which of the following logic gates can be used to realize all possible combinational Logic functions. (A)OR gates only (B) NAND gates only (C)EX-OR gates only (D)NOR gates only For the combinational circuit shown in figure, Nor ua —fa—p. TOR 3,_—) oR Which of the following truth table is correct? oz] ef fofofo] fofo] TPT TT TTT Yo TPo]o Tpopo Taya TPT TT () [A] BIZ (D) | A] BIZ Tp op o vp opt TPT pA TTPO aE . Th To _ Boolean expression for the output of XNOR (equivalence) logic gate with inputs A and B is (A) AB+AB (B) AB+AB (C) (A+ B)(A+B) (D) (A+ B)(A+B) Q7 Q8 Qo Q10 Quin Qu2 Identify the logic function performed by the circuit shown in figure ) > (A) Exclusive OR (B) Exclusive NOR (C)NAND (D)NOR The output of a logic gate is ‘1° when all its inputs are at logic ‘0°. The gate is either (A)a NAND or an EX-OR gate (B)a NOR or an EX-NOR gate. (C) an OR or an EX-NOR gate. (D)an AND or an EX-OR gate A ring oscillator consisting of 5 inverters is running at a frequency of 1.0 MHz. The propagation delay per gate is nsec. Any Boolean function can be realized using only (A)NAND gate (B) AND gate (C)OR gate (D)NOT gate The minimum number of NAND gates required to implement the Boolean function A+AB+ ABC is equal to (B)I (D)7 (A)Zero (4 If A and B are the inputs to a logic gate, then match the logic with its output (i) A+B (a) NAND. (b) NOR (©) XNOR (@) AND. (A)a-ii, b-i, e-ili, d-iv (B)adii, b-iv, c-iti, d-i (Chai, bei, coi, dil (D)a-iii, b-ii, c-iv, diDigital Electronics Qu3 Qu4 Qus Q.16 Qu7 Qs Qs The output of the logic gate in figure is, Q.20. The complete set of only those Logic Gates —p> designated as Universal Gates is (A)NOT, OR and AND Gates. (B)XNOR, NOR and NAND Gates. (ayo BI (C)NOR and NAND Gates. (a4 ()A (D)XOR, NOR and NAND Gates. What happens when a bit ~string is XORed_ Q.21 The output ¥ of the logic circuit given below with itself n — times as shown a [B0(BO(BO(B....n times)] x4 : (A) Complements when miseven [p—D- (B) Complements when n is odd Ml (B)o (C) Divides by 2° always ox (DF (D) Remains unchanged when n is even Q.22 Which one of the following circuits is NOT Which of the following expression is not equivalent to a 2-input XNOR (exclusive equivalent to x? aay gate? (A)x NAND x (B)x NOR x (C)x NAND I (D)x NOR I =p The output of a logic gate is “1” when all its @) inputs are at logic “0”. The gate is either SD (A)A NAND or an EX-OR gate. Pay (B) A NOR or an EX-OR gate. aay > (©) An AND or an EX-NOR gate, (D)A NOR or an EX-NOR gate. [, If the input to the digital circuit consisting of opty D> a cascade of 20 X-OR gates is X, then the output Y is equal to Q.23. The logic evaluated by the circuit at the 1 output is PPD ps “=D Dame xe ye (ayo (By A Ox (Dx : [H The expression Y = AB is equivalent to =e are (A) AT +8 (A) 448 (B) AB+A eee (C) AtB (D) AB (B)(X+Y)XY The Boolean function ¥ = AB + CD is to be oonxy realized using only 2-input NAND gates. (D) RY +Ax7 4x4 ‘The minimum number of gates required is FF — 2 ®)3 gates required to implement a 2-input XOR 4 (ws gate isQ.25 (a4 (B)s (6 (D)7 In the logic circuit shown in the figure, ¥ is given by 4a s— [> st > pol (A) ¥ = ABCD (B) ¥ = (4+. BY(C+D) (C)¥ =4+B+C+D (D) ¥ = AB+CD Q.26 The Boolean function (X,Y) realized by the given circuit is x o (A) Fy + AxF (B) XY + XY (C) X+Y¥ (D) X-¥ Logic Gates Q.27 Find the fundamental frequency of the ring oscillator given below. Propagation delay of each inverter is 10ps. Dopo Do % (A)8 GHz (B) 16 GHz (C)8 MHz (D) 16 MHz eee