Lectures: SEQUENTIAL CIRCUITS

VLSI Design
(Subject Code- ECC602)

Instructor: Hemanta Kumar Mondal, PhD

National Institute of Technology Durgapur

Regenerative circuit
 Regenerative circuit
Bistable circuits
Two stable states
Most widely used and important
All basic latch, flip-flop circuits,
registers, and memory elements
Monostable circuits
Only one stable operating point
Astable circuits
No stable operating point
Oscillate, without settling into a
stable operating mode

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Sequencing

 Combinational logic
 output depends on current inputs

 Sequential logic
 output depends on current and previous inputs
 Requires separating previous, current, future
 Called state or tokens
 Ex: FSM, pipeline

clk clk clk clk

in out
CL CL CL

Finite State Machine Pipeline

11: Sequential Circuits 3

 SR latch circuit
• The bi-stable element
– Consisting two cross-coupled inverters has two stable operating states
– Preserving its state as long as the power supply is provided
• CMOS SR latch
– Having two triggering inputs, S and R
• Triggering the circuit from one operating
point to the other
– SR flip-flop
• Two stable states can be switched back and
forth
– Consisting
• Two CMOS NOR2 gates
– One input cross-couple to the output of
other NOR gate
– Another input enables triggering of the
circuit
SR latch circuit
• The SR latch has two complementary outputs, Q and –Q
– Q=1  in its “set” state
– Q=0  in its “reset” state
• Gate level schematic
– Two NOR2 gates
– If both inputs =“0”
• Operating like the simple cross-coupled bistable
element
• Holding either one of its two stable operating
points (states) as determined by the previous
inputs
– If S=1
• Forcing the output Q=1
– If R=1
• Forcing the output Q=0
– S=1 and R=1, not allowed
Clocked SR latch
• A clocked NOR-based SR latch
– CK=0
• The input signal have no influence upon the circuit response
• Output hold its current state
– CK=1
• S and R inputs are permitted to reach the SR latch
– The circuit is strictly level-sensitive during active clock phases
• Any changes occurring in the S and R input voltage when the CK level is equal
to “1”
Active low
• The changes in the input signal levels will be ignored when the clock is equal
to logic “1”
• The input will influence the outputs only when the clock is active, i.e., CK=0
The clocked NAND-based SR latch
• Both the input signals and the CK signal are active high
• CK=1
– S=1, R=0  Q will be set
– S=0, R=1  Q will be reset
• CK=0
– The latch preserves its state
• Drawback
– The transistor count is higher than the active low version shown in Fig. 8.17
Sequencing Elements
 Latch: Level sensitive
 a.k.a. transparent latch, D latch
 Flip-flop: edge triggered
 A.k.a. master-slave flip-flop, D flip-flop, D register
 Timing Diagrams clk clk

 Transparent when CLK = High

Latch

Flop
D Q D Q

 Opaque when CLK = Low clk

 Edge-trigger D

Q (latch)

Q (flop)

11: Sequential Circuits 9

Latch Design

 Pass Transistor Latch

 Pros 
+ Tiny
+ Low clock load D Q
 Cons
Used in 1970’s
 Vt drop
 Nonrestoring (producing outputs that has not been restored or regenerated)

11: Sequential Circuits 10

Latch Design

 Transmission gate
+ No Vt drop 
- Requires inverted clock (Extra H/W)
D Q

• It only requires two transistors but it is a nonrestoring circuit.

• If the input is noisy or otherwise degraded, the output will receive the same noise.

11: Sequential Circuits 11

Advantages of TG over PT

 Transmission Gate Logic : The transmission gate logic is used to solve the voltage
drop problem of the pass transistor logic.

 This technique uses the complementary properties of NMOS and PMOS transistors.
i.e. NMOS devices passes a strong '0' but a weak '1' while PMOS transistors pass a
strong '1' but a weak '0'.

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Latch Design

 Inverting buffer 
 Inverted output
X
D Q




D Q

11: Sequential Circuits 13

Latch Design
 Tristate feedback
+ Static

X
D Q
 Static latches are now essential


because of leakage

• A tri-state inverter is similar to a inverter, but it adds an additional "enable" input that controls
whether the primary input is passed to its output or not.
• The output is actively driven from VDD or GND, so it is a restoring logic gate.

11: Sequential Circuits 14

Latch Design

 Buffered input
+ Noninverting 
X
D Q



11: Sequential Circuits 15

Latch Design

 Buffered output  Q

X
D



 Widely used in standard cells

+ Very robust (most important) 
- Rather large
- Rather slow (1.5 – 2 FO4 delays)
- High clock loading

11: Sequential Circuits 16

Latch Design

 Datapath latch
 Q
+ smaller
+ faster X
D
- unbuffered input



11: Sequential Circuits 17

Flip-Flop Design

 Flip-flop is built as pair of back-to-back latches

 
X
D Q

 

  Q

X
D Q
 
 

 

11: Sequential Circuits 18

Example_1 of Setup and Hold time
 Problem: In order to work correctly, what should be the Setup and Hold time at Input A
in the following Circuit. Also find out the maximum operating frequency for this circuit.
(Note: Ignore Wire delay). Where Tsu- Setup time; Thd- Hold Time; Tc2q-Clock-to-Q
delay.
Example of Setup and Hold time Static
 Step1: Find out the maximum Register to register Delay.

 Timing path: Timing paths can be divided as per the type of signals (e.g clock signal, data signal etc).

 Types of Paths for Timing analysis

 Data path
 Clock path

 Data path
 Start Point
 Input port of the design (because the input data can be launched from some external source).
 Clock pin of the flip-flop/latch/memory (sequential cell)
 End Point
 Data input pin of the flip-flop/latch/memory (sequential cell)
 Output port of the design (because the output data can be captured by some external sink)
Example of Setup and Hold time Static
 Data Paths: 4 types of data path
 Input pin/port to Register(flip-flop).
 Input pin/port to Output pin/port.
 Register (flip-flop) to Register (flip-flop)
 Register (flip-flop) to Output pin/port

 PATH1- starts at an input port and ends at the data input of a sequential element. (Input port to Register)
 PATH2- starts at the clock pin of a sequential element and ends at the data input of a sequential element.
(Register to Register)
 PATH3- starts at the clock pin of a sequential element and ends at an output port.(Register to Output port).
 PATH4- starts at an input port and ends at an output port. (Input port to Output port)
Clock Path
 Clock path the starts from the input port/pin of the design which is specific for the Clock input

 And the end point is the clock pin of a sequential element. In between the Start point and the
end point there may be lots of Buffers/Inverters/clock divider.
Example of Setup and Hold time Static
 Register to register delay (Trrd) = Tc2q + Tgd + Twd + Tsu

 Where, Tc2q = Clk-to-Q delay

Tgd = Cell/ gate delay
Twd = All wire delay
TSU = Setup time

 What is Setup and Hold time?

Setup time
 Setup time is the minimum amount of time the data signal should be
held steady before the clock event so that the data are reliably sampled
by the clock. This applies to synchronous circuits such as the flip-flop.
 Or in short we can say that the amount of time the Synchronous input
(D) must be stable before the active edge of the Clock.
 The Time when input data is available and stable before the clock pulse
is applied is called Setup time.
Hold Time
 Hold time is the minimum amount of time the data signal should be
held steady after the clock event so that the data are reliably sampled.
This applies to synchronous circuits such as the flip-flop.
 Or in short we can say that the amount of time the synchronous input
(D) must be stable after the active edge of clock.
 The Time after clock pulse where data input is held stable is called hold
time.
Various ways to fix Setup violations
 Reduce the amount of buffering in the path
 Replace buffers with 2 Inverters place farther apart
 Increase Driver Size or say increase Driver strength (also known as
upsize the cell)
 Insert Buffers or repeaters
 Adjust cell position in layout.
 Clock skew:
Various ways to fix hold time violations
 By Adding delays
 Decreasing the size of certain cells in the data path.

 Following points are recommended while fixing setup and hold violations.
 Make modification to the data path only.
 First try to fix setup violation as much as possible. Then later on start fixing hold
violation.
 In general, hold time will be fixed during back-end work (during PNR) while
building clock tree. If u r a front-end designer, concentrate on fixing setup time
violations rather than hold violations.
 Fix all the hold violation, if you have to choose between setup and hold.
Example of Setup and Hold time Static
 Step1: Find out the maximum Register to register Delay.
 Data arrival time is the time required for data to propagate through source flip flop,
travel through combinational logic and routing and arrive at the destination flip-flop
before the next clock edge occurs.
 Register to register delay = Clk-to-Q delay + Cell/ gate delay + All wire delay + Setup
time

 Max Register to Register Delay = 16ns (Wire delay is neglected)

 Note: There are 2 register paths. We have to pick maximum one.
 Step 2: Find Out Setup Time
 A setup time = Setup time of Flipflop + Max (Data path Delay) - min(Clock path Delay)
= (Setup time of Flipflop + A2D max delay) - (Clk path min delay)
= Tsu + (Tpd U7 + Tpd U3 + wire delay) - Tpd U8
= 3 + (1+8 ) - 2 = 10 ns
Example of Setup and Hold time Static
 Step 2: Find Out Setup Time
 A setup time = Setup time of Flipflop + Max (Data path Delay) - min(Clock path Delay)
= (Setup time of Flipflop + A2D max delay) - (Clk path min delay)
= Tsu + (Tpd U7 + Tpd U3 + wire delay) - Tpd U8
= 3 + (1+8 ) - 2 = 10 ns

Note: Since for setup calculation we need maximum Data path delay, We have
choosen 2nd for our calculation.
Example of Setup and Hold time Static
 Step 3: Find Out Hold Time:
 A hold time = Hold time of Flipflop + max(Clock path Delay) - min( Data path delay)
=( Hold time of Flipflop + Clk path max delay) - (A2D min delay)
= Thd + Tpd U8 - (Tpd U7 + Tpd U4+wire delay)
= 4 + 2 - (1+7 ) = -2 ns
Note: For hold time we need minimum data path, so we have picked first Data path.
 Step 4: Find out Clock to Out Time:
 Clock to Out
= Cell delay of U8 + Clk-to-Q delay of FlipFlop+ Cell delay of U5+ Cell delay of U6 + (all
wire delay)
= Tpd U8+ U2 Tc2q + U5 Tpd + U6 Tpd
= 2 + 5 + 9 + 6 = 22 ns
Example of Setup and Hold time Static
 Step 4: Find out Clock to Out Time:

 Clock to Out

= Cell delay of U8 + Clk-to-Q delay of FlipFlop+ Cell delay of U5+ Cell delay of U6+ (all
wire delay)

= Tpd U8+ U2 Tc2q + U5 Tpd + U6 Tpd

= 2 + 5 + 9 + 6 = 22 ns

Note: Since in this case the clk –to-Q path for both Flipflop is same, we can consider any path. But
in some other circuit where the delay is different for both the paths, we should consider Max delay
path.
Example of Setup and Hold time Static
 Step 5: Find Pin to Pin Combinational Delay (A to Y delay)
 Pin to Pin Combinational Delay (A to Y)
= U7 Tpd + U5 Tpd + U6 Tpd
= 1 + 9 + 6 = 16 ns

 Step 6: Find Out Max Clock Frequency:

Max Clock Freq. = 1/ Max (Reg2reg, Clk2Out, Pin2Pin)
= 1/ Max (16, 22, 16)
= 45.5 Mhz
 Summary
Parameter Description Min Max Units
Tclk Clock Period 22 ns
Fclk Clock Frequency 45.5 Mhz
Atsu A setup time 10 ns
Athd A hold time -2 ns
A2Y A to Y Tpd 16 ns
Ck2Y Clock to Y Tpd 22 ns
Setup and Hold Slack
 Data Arrival Time:
 This is the time required for data to travel through data path.
 Data Required Time:
 This is the time taken for the clock to traverse through clock path.

 Setup and hold slack is defined as the difference between data required
time and data arrival time.
Clock Skew
 Clock skew (sometimes called timing skew) is a phenomenon in
synchronous digital systems in which the same sourced clock
signal arrives at different components at different times.
 The instantaneous difference between the readings of any two clocks is
called their skew.
Clock Skew
 We have assumed zero clock skew
 Clocks really have uncertainty in arrival time
 Decreases maximum propagation delay
 Increases minimum contamination delay

The propagation delay: is the maximum time from when an input changes until the output or
outputs reach their final value.

The contamination delay: is the minimum time from when an input changes until any output
starts to change its value.

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Example_2: Setup or Hold Violation?

 In the following circuit, find out whether there is any Setup or Hold Violation?

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Example_2: Setup or Hold Violation?
 Hint:

 Hold Analysis:

 When a hold check is performed, we have to consider two things-

 Minimum Delay along the data path
 Maximum Delay along the clock path

 If the difference between the data path and clock path is negative, then a timing violation has occurred.

 Setup Analysis:

 When a setup check is performed, we have to consider two things-

 Maximum Delay along the data path
 Minimum Delay along the clock path

 If the difference between the data path and clock path is negative, then a timing violation has occurred.

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