ECE 342

Electronic Circuits

Lecture 33
CMOS Characteristics

Jose E. Schutt-Aine
Electrical & Computer Engineering
University of Illinois
jesa@Illinois.edu

ECE 342 – Jose Schutt‐Aine 1
 Digital Circuits

VIH: Input voltage at high state  VIHmin

VIL: Input voltage at low state  VILmax
VOH: Output voltage at high state  VOHmin
VOL: Output voltage at low state  VOLmin

Likewise for current we can define

Currents into input Currents into output

IIH  IIHmax IOH  IOHmax

IIL  IILmax IOL  IOLmax

ECE 342 – Jose Schutt‐Aine 2
 Voltage Transfer Characteristics (VTC)
The static operation of a logic circuit is determined by its VTC

• In low state: noise margin is

NML

NM L  VIL  VOL
• In high state: noise margin is
NMH
NML NMH
NM H  VOH  VIH
• An ideal VTC will maximize noise VIL and VIH are the points where the
margins slope of the VTC=-1

Optimum: NM L  NM H  VDD / 2
ECE 342 – Jose Schutt‐Aine 3
 Switching Time & Propagation Delay

input

output

ECE 342 – Jose Schutt‐Aine 4
 Switching Time & Propagation Delay

tr=rise time (from 10% to 90%)

tf=fall time (from 90% to 10%)
tpLH=low-to-high propagation delay
tpHL=high-to-low propagation delay

1
Inverter propagation delay: t p   t pLH  t pHL 
2

ECE 342 – Jose Schutt‐Aine 5
 VTC and Noise Margins
For a logic-circuit family employing a 3-V supply, suggest an
ideal set of values for Vth, VIL, VIH, VOH, NML, NMH. Also, sketch
the VTC. What value of voltage gain in the transition region
does your ideal specification imply?

Ideal 3V logic implies:

VOH  VDD  3.0V ; VOL  0.0V

Vth  VDD / 2  3.0 / 2  1.5V ;

VIL  VDD / 2  1.5V ; VIH  VDD / 2  1.5V

ECE 342 – Jose Schutt‐Aine 6
 VTC and Noise Margins
NM H  VOH  VIH  3.0  1.5  1.5V

NM L  VIL  VOL  1.5  0.0  1.5V

Inverting transfer characteristics

The gain in the transition region is:

VOH  VOL  / VIH  VIL    3.0  0.0  / 1.5  1.5

 3/ 0  V /V

ECE 342 – Jose Schutt‐Aine 7
 CMOS Noise Margins
When inverter threshold is at VDD/2, the noise margin NMH and NML are
equalized

3 2 
NM H  NM L   VDD  Vth 
8 3 

: noise margin for high input

NML: noise margin for low input
Vth: threshold voltage

Noise margins are typically around 0.4 VDD; close to half power-supply voltage 
CMOS ideal from noise-immunity standpoint

ECE 342 – Jose Schutt‐Aine 8
CMOS Inverter VTC

QP and QN are
matched

ECE 342 – Jose Schutt‐Aine 9
 CMOS Inverter VTC
Derivation
 Assume that transistors are matched
 Vertical segment of VTC is when both QN and QP are saturated
 No channel length modulation effect  = 0
 Vertical segment occurs at vi=VDD/2
 VIL: maximum permitted logic-0 level of input (slope=-1)
 VIH: minimum permitted logic-1 level of input (slope=-1)
To determine VIH, assume QN in triode region and QP in saturation region

1 2 1
 vI  Vt  vo  vo  VDD  vI  Vt 
2

2 2
Next, we differentiate both sides relative to vi

dvo dvo
 vI  Vt   vo  vo   VDD  vI  Vt 
dvI dvI
ECE 342 – Jose Schutt‐Aine 10
 CMOS Inverter VTC

Substitute vi=VIH and dvo/dvi = -1

VDD
vo  VIH 
2
After substitutions, we get
1
VIH   5VDD  2Vt 
8
Same analysis can be repeated for VIL to get
1
VIL   3VDD  2Vt 
8

ECE 342 – Jose Schutt‐Aine 11
 CMOS Inverter Noise Margins
1
VIH   5VDD  2Vt 
8
1
VIL   3VDD  2Vt 
8
1
NM H   3VDD  2Vt 
8

1 Symmetry in VTC  equal

NM L   3VDD  2Vt  noise margins
8

ECE 342 – Jose Schutt‐Aine 12
 Matched CMOS Inverter VTC

CMOS inverter can be made to switch at specific threshold voltage by

appropriately sizing the transistors

W  n  W 
    
 L  p  p  L n
Symmetrical transfer
characteristics is obtained via
matching  equal current driving
capabilities in both directions
(pull-up and pull-down)

ECE 342 – Jose Schutt‐Aine 13
 VTC and Noise Margins - Problem
An inverter is designed with equal-sized NMOS and PMOS
transistors and fabricated in a 0.8-micron CMOS technology
for which kn’ = 120 A/V2, kp’ = 60 A/V2, Vtn =|Vtp|=0.7 V, VDD
= 3V, Ln=Lp = 0.8 m, Wn = Wp = 1.2 m, find VIL, VIH and the
noise margins.

Equal sizes NMOS and PMOS, but kn’=2kp’

Vt = 0.7V

For VIH: QN in triode and QP in saturation

W   1 2 1 ' W 
k   VI  Vt Vo  Vo   k p   VDD  VI  Vt 
' 2
n
 L n  2  2  L p

ECE 342 – Jose Schutt‐Aine 14
 VTC and Noise Margins – Problem (cont’)

4 VI  Vt Vo  2V  VDD  VI  Vt 

2 2
o (1)

Differentiating both sides relative to VI results in:

 Vo Vo
: 4 VI  Vt   4Vo  4Vo  2 VDD  VI  Vt  (1)
VI VI VI

Substitute the values together with:

Vo
VI  VIH and  1
VI

ECE 342 – Jose Schutt‐Aine 15
 VTC and Noise Margins – Problem (cont’)

4 VIH  0.7  1  4Vo  4Vo  2 VIH  3  0.7 

8Vo  7.4 (2)

VIH   1.33Vo  1.23
6

From (1) : 4 VIH  0.7 Vo  2V   3  VIH  0.7 

2 2
o

4 VIH  0.7 Vo  2V   2.3  VIH 

2 2
o (3)

solving (2) & (3) : 1.55Vo2  4.97Vo  1.14  0

 Vo  0.22 V VIH  1.52 V

ECE 342 – Jose Schutt‐Aine 16
 VTC and Noise Margins – Problem (cont’)
For VIL: QN is in saturation and QP in triode

1 ' W  ' W   1 2
kn   VI  Vt   k p   VDD  VI  Vt VDD  Vo   VDD  Vo  
2

2  L n  L p  2 

1
VI  0.7    3  VI  0.7   3  Vo    3  Vo 
2 2
(1)
2
1
VI  0.7    2.3  VI   3  Vo    3  Vo 
2 2

2
  Vo  Vo
 2 VI  0.7    2.3  VI       3  Vo    3  Vo 
VI  VI  VI

ECE 342 – Jose Schutt‐Aine 17
 VTC and Noise Margins – Problem (cont’)
Vo
VI  VIL and  1
VI
2VIL  1.4  2.3  VIL  3  Vo  3  Vo
2
VIL  Vo  1.15
3
1
From (1) : VIL  0.7    2.3  VIL   3  Vo    3  Vo 
2 2

2
1
 0.66Vo  1.85   3.45  0.66Vo  3  Vo    3  Vo 
2 2

2
ECE 342 – Jose Schutt‐Aine 18
 VTC and Noise Margins – Problem (cont’)
Vo  2.96 V VIL  0.81 V

Noise Margins:

NM H  3  1.52  1.48 V

NM L  0.81  0  0.81 V

Since QN and QP are not matched, the VTC is not

symmetric

ECE 342 – Jose Schutt‐Aine 19