6.

Finite State Machines

6.004x Computation Structures

Part 1 – Digital Circuits

Copyright © 2015 MIT EECS

6.004 Computation Structures L6: Finite State Machines, Slide #1

 Our New Machine

Next
k
k State
State
Registers Current
State Combinational
Clock Logic
m n
Input Output

• Engineered cycles •  Acyclic graph

• Works only if dynamic •  Obeys static discipline
discipline obeyed
•  Can be exhaustively enumerated
• Remembers k bits for a by a truth table of 2k+m rows and
total of 2k unique k+n output columns
combinations

6.004 Computation Structures L6: Finite State Machines, Slide #2

 A Simple Sequential Circuit…

Lets make a digital binary Combination Lock:

Specification:
•  One input ( “0” or “1”)
IN
Lock U
•  One output (“Unlock”
CLK
signal)
How many
state bits
•  UNLOCK is 1 if and only if:
do I need?
Last 4 inputs were the
“combination”: 0110

6.004 Computation Structures L6: Finite State Machines, Slide #3

 Abstraction du jour: Finite State Machines

m
inputs Clocked n
FSM outputs

A FINITE STATE MACHINE has

• k STATES: S1 … Sk (one is “initial” state)
• m INPUTS: I1 … Im
• n OUTPUTS: O1 … On
• Transition Rules: s’(s, I) for each state s and input I
• Output Rules: Out(s) or Out(s, I) for each state s
and input I
6.004 Computation Structures L6: Finite State Machines, Slide #4
 State Transition Diagram Why do these
go to S0 and S01?

0
1
SX S0 S01 S011 S0110
1 U=0 0 U=0 1 U=0 1 U=0 0 U=1

0 0
1

Heavy circle
Designing our lock … Means
INITIAL state
• Need an initial state; call it SX. NAME
of state
• Must have a separate state for 0
XXX
each step of the proper entry
U=0
sequence OUTPUT INPUT
• Must handle other (erroneous) when in this causing
state transition
entries

6.004 Computation Structures L6: Finite State Machines, Slide #5

 Valid State Diagrams
1/0
1

S1 S3 S1 S3
0 1 1 1/0
0 0/0 0/1
0
S2 Inputs/outputs S2 0/0
0 0
1 1/0

MOORE Machine: MEALY Machine:

Outputs on States Outputs on Transitions

Arcs leaving a state must be:

(1) mutually exclusive
–  can’t have two choices for a given input value
(2) collectively exhaustive
–  every state must specify what happens for each possible
input combination. “Nothing happens” means arc back to
itself.
6.004 Computation Structures L6: Finite State Machines, Slide #6
 State Transition Diagram as a Truth Table
0
1
SX S0 S01 S011 S0110
1 U=0 0 U=0 1 U=0 1 All state transition
U=0 0 U=1

0 0 diagrams can be
1
described by truth
IN Current State Next State Unlock tables…
0 000 SX S0 001 0
1 000 SX SX 000 0 Binary encodings are
0 001 S0 S0 001 0
assigned to each
1 001 S0 S01 011 0
0 011 S01 S0 001 0 state (a bit of an art)
1 011 S01 S011 010 0
0 010 S011 S0110 100 0 The truth table can
1 010 S011 SX 000 0
0 100 S0110 S0 001 1 then be simplified
1 100 S0110 S01 011 1 using the reduction
The assignment of codes to
techniques we
states can be arbitrary, however, learned for
if you choose them carefully you combinational logic
can greatly reduce your logic
requirements.
6.004 Computation Structures L6: Finite State Machines, Slide #7
 Now Put It In Hardware!
We assume 4 inputs ⇒ 24 locations,
inputs are each location supplies
synchronized 4 bits
with clock…
unlock
IN
ROM
16x4
Current Next
state state

3 3

5 states
⇒ 3-bit encoding

Trigger update periodically (“clock”)

6.004 Computation Structures L6: Finite State Machines, Slide #8
 Discrete State, Discrete Time

inputs outputs
ROM
Two design choices:
(1) outputs only depend on state (Moore)
STATE NEXT (2) outputs depend on inputs + state (Mealy)
s s
s state bits ⇒ 2s possible states

Clock

STATE

NEXT
Clock Clock Clock Clock Clock
Period Period Period Period Period
1 2 3 4 5

6.004 Computation Structures L6: Finite State Machines, Slide #9

 Housekeeping Issues…

1. Initialization? Clear the memory?

inputs ROM outputs
or 2. Unused state encodings?
gates - waste ROM (use gates)
STATE NEXT - what does it mean?
s s - can the FSM recover?
0

initial 3. Choosing encoding for state?

1

reset
4. Synchronizing input changes with
U state update?

IN

CLK
Now, that’s a funny
looking state machine

6.004 Computation Structures L6: Finite State Machines, Slide #10

 FSM States

1. What can you say about ROM

the number of states?
k k

x y z
2. Same question: m n
States States

3. Here’s an FSM. Can

you discover its rules?

6.004 Computation Structures L6: Finite State Machines, Slide #11

 What’s My Transition Diagram?

1
0=OFF, 0 1 vs.
1=ON? 0
1 1 1 1
"1111" = 0 1
Surprise! 01 0 0 0

•  If you know NOTHING about the FSM, you’re never sure!

•  If you have a BOUND on the number of states, you can

discover its behavior:

K-state FSM: Every (reachable) state can be

reached in < k steps.
BUT ... FSMs may be equivalent!

6.004 Computation Structures L6: Finite State Machines, Slide #12

 FSM Equivalence

1 1 1 1 1
0 1 vs. 0 1
0 0 0 0 0

ARE THEY DIFFERENT?

NOT in any practical sense! They are EXTERNALLY
INDISTINGUISHABLE, hence interchangeable.

FSMs are EQUIVALENT iff every input

sequence yields identical output sequences.

ENGINEERING GOAL:
• HAVE an FSM which works...
• WANT simplest (ergo cheapest) equivalent FSM.

6.004 Computation Structures L6: Finite State Machines, Slide #13

 Let’s Build a RoboAnt

•  SENSORS: antennae L and R, each 1 if in

8 legs? contact with something.
•  ACTUATORS: Forward Step F, ten-degree turns
TL and TR (left, right).

GOAL: Make our ant smart enough to get out of a maze like:

STRATEGY: "Right antenna to the wall"

6.004 Computation Structures L6: Finite State Machines, Slide #14
 Lost In Space

Action: Go forward until we hit something.

LOST L+R
F

__
LR

“lost” is the
initial state

6.004 Computation Structures L6: Finite State Machines, Slide #15

 Bonk!

Action: Turn left (CCW) until we don’t touch anymore

L+R

LOST L+R RCCW

F TL

_ _
__ LR
LR

6.004 Computation Structures L6: Finite State Machines, Slide #16

 A Little to the Right…

Action: Step and turn right a little, look for wall

L+R

LOST L+R RCCW

F TL

_ _ R
__ LR
LR

Wall1
_
TR,F R

6.004 Computation Structures L6: Finite State Machines, Slide #17

 Then a Little to the Left

Action: Step and turn left a little, till not touching (again)
L+R _
LR
LOST L+R RCCW Wall2
F TL L TL,F

_ _ R
__ LR __
LR LR

Wall1
_
TR,F R

6.004 Computation Structures L6: Finite State Machines, Slide #18

 Dealing With Outside Corners

Action: Step and turn right until we hit perpendicular wall

L+R _
LR
LOST L+R RCCW Wall2
F L TL,F
TL Hey, this
_ _ R
might
__ LR
LR
__ even work!
LR
R _
R
Wall1 Corner
_
TR,F R TR,F

6.004 Computation Structures L6: Finite State Machines, Slide #19

 Equivalent State Reduction

Observation: two states are equivalent if

1. Both states have identical outputs; AND
2. Every input ⇒ equivalent states.

Reduction Strategy:
Find pairs of equivalent states, MERGE them.

L+R _
LR
LOST L+R RCCW Wall2
F TL L TL,F

_ _ R
__ LR __
LR LR
R _
R
Wall1 Corner
_
TR,F R TR,F

6.004 Computation Structures L6: Finite State Machines, Slide #20

 An Evolutionary Step

Merge equivalent states Wall1 and Corner into a single new,

combined state.

L+R _
LR
LOST L+R RCCW Wall2
F TL L TL,F

_ _ R
__ LR __
LR LR

Wall1
TR,F

_
R

Behaves exactly as previous (5-state) FSM, but requires half the

ROM in its implementation!
6.004 Computation Structures L6: Finite State Machines, Slide #21
 Building The Transition Table

S L R | S’ TR TL F
-------+-----------
L+R 00 0 0 | 00 0 0 1
00 0 1 | 01 0 0 1
LOST L+R RCCW 00 1 0 | 01 0 0 1
F TL 00 1 1 | 01 0 0 1
01 0 1 | 01 0 1 0
__ 01 1 0 | 01 0 1 0
LR 01 1 1 | 01 0 1 0

6.004 Computation Structures L6: Finite State Machines, Slide #22

 Implementation Details

S1’ S1S 0
S L R | S’ TR TL F 00 01 11 10
-------+----------- 00 0 1 1 1
00 0 0 | 00 0 0 1 LR 01 0 0 1 1
00 1 - | 01 0 0 1 11 0 0 0 1
LOST
00 - 1 | 01 0 0 1 10 0 0 0 1
01 1 - | 01 0 1 0
S1! = S1 S 0 + LS1 + L RS 0
RCCW 01 - 1 | 01 0 1 0
01 0 0 | 10 0 1 0
10 – 0 | 10 1 0 1 S0’ S1S 0
WALL1 00 01 11 10
10 – 1 | 11 1 0 1
00 0 0 0 0
11 1 - | 01 0 1 1
LR 01 1 1 1 1
WALL2 11 0 0 | 10 0 1 1
11 1 1 1 1
11 0 1 | 11 0 1 1
10 1 1 1 0
Complete Transition table
S 0! = R + L S1 + LS 0
6.004 Computation Structures L6: Finite State Machines, Slide #23
 Ant Schematic

6.004 Computation Structures L6: Finite State Machines, Slide #24

 FSMs All the Way Down?
• More than ants:
Swarming, flocking, and schooling
Did we all descend from FSMs???
can result from collections of very
simple FSMs
I prefer to think we
ascended…
• Perhaps most physics:
Cellular automata, arrays of simple
FSMs, can more accurately model
fluids than numerical solutions to
PDEs

• What if:
We replaced the ROM with a RAM
and have outputs that modify the
RAM?

... You'll see FSMs for the rest of your

life!
6.004 Computation Structures L6: Finite State Machines, Slide #25
 The World Doesn’t Run on Our Clock!
But what
What if each button about the
input is an 0 dynamic
asynchronous 0/1 0 1 B0 discipline?
level? 1 B1Lock U

To build a system with asynchronous inputs, we have to

break the rules: we cannot guarantee that setup and hold
time requirements are met at the inputs!

So, we need a “synchronizer” at each input:

0 U(t) S(t) Valid except for

1 (Unsynchronized) (Synchronized)
Synchronizer brief periods
following active
clock edges
Clock
6.004 Computation Structures L6: Finite State Machines, Slide #26
 The Bounded-time Synchronizer
A classic problem
UNSOLVABLE
For NO finite
IN: at tIN IN S values of tE and
Sync
tD is this spec
CLK: at tC CLK
realizable, even
with reliable
components!
Synchronizer specifications:
•  finite tD (decision time) IN: >tE >tE
•  finite tE (allowable error)
CLK:
•  value of S at time tC+tD: tD tD tD
1 if tIN < tC – tE S:
0 if tIN > tC + tE
0, 1 otherwise CASE 1 CASE 2 CASE 3

6.004 Computation Structures L6: Finite State Machines, Slide #27

 Unsolvable? That can’t be true…

DECISION TIME is TPD of register.

Let’s just use a D Register:
ALLOWABLE ERROR is max(tSETUP,
tHOLD)
IN: at tIN D Q
Our logic:

CLK: at tC TPD after TC, we’ll have

Q=1 iff tIN + tSETUP < tC
Q=0 iff tC + tHOLD < tIN
We’re lured by the digital Q=0 or 1 otherwise.
abstraction into assuming
that Q must be either 1 or
0. But let’s look at the IN D Q D Q
master slave
input latch in the flip flop
when IN and CLK change at G G
about the same time... CLK

6.004 Computation Structures L6: Finite State Machines, Slide #28

 The Mysterious Metastable State

Vin 0 VTC of
Q “closed” latch
Vout Y
1 Vout Latched in
a ‘1’ state

Latched in
Recall that the latch output is an undefined
state VTC of feedback
the solution to two
path (Vin=Vout)
simultaneous constraints:
1. The VTC of path
thru MUX; and Latched in
a ‘0’ state
2. Vin = Vout Vin

In addition to our expected stable solutions, we find an unstable

equilibrium in the forbidden zone called the “Metastable State”

6.004 Computation Structures L6: Finite State Machines, Slide #29

 Metastable State: Properties
1.  It corresponds to an invalid
logic level.
2.  It’s an unstable equilibrium; a
small perturbation will cause it
to move toward a stable 0 or 1. metastable
state
3.  It will settle to a valid 0 or 1...
eventually.
4.  BUT – depending on how close
it is to the Vin=Vout “fixed point” If metastable at t0:
of the device – it may take
arbitrarily long to settle out. •  p(metastable at t0+T) > 0
for finite T
5.  EVERY bistable system
exhibits at least one •  p(metastable at t0+T)
metastable state! decreases exponentially
with increasing T

6.004 Computation Structures L6: Finite State Machines, Slide #30

 Solution: Delay Increases Reliability
A metastable state here
Extra registers between will probably resolve itself
to a valid level before it
the asynchronous input gets into my circuit.
and your logic are the
best insurance against
metastable states. In Out
DQ DQ Combinational DQ
For higher clock rates, logic

consider adding Clk

additional registers.
And one here will almost
certainly get resolved.

Quarantine time In Out

reduces p(metastable) DQ DQ DQ Combinational DQ
logic

Clk

6.004 Computation Structures L6: Finite State Machines, Slide #31