Divisor De Frecuencia De 50m A 5k “11111001” when “001”; contador + 1; if rising_edge(clk) then

entity …….. is …………………………….. end case; cuenta <= cuenta + 1;

port(clk, e0,e1: in std_logic; “11111000” when others; end if; if cuenta = 25000000 then
z: out std_logic); u1: process(clk) end process; cuenta <= (others => ‘0’);
end ……; begin process (ep, stop) x <= not x;
architecture …. of ….. is if rising_edge(clk) then begin end if;
signal cuenta: std_logic_vector cuenta <= cuenta + 1; es <= ep; end if;
(13 downto 0); if cuenta = 25000000 then case ep is end process;
begin cuenta <= (others =>’0’); when s0 => r<=’0’; a<=’0’; v<=’1’; process (clr, x)
process x <= notx; if stop=’1’ then begin
begin end if; es <= s1; if clr = ‘1’ then
if rising_edge(clk) then end if; else es <= s0; end if; uni <= “0000”;
cuenta <= cuenta + 1; end process u1; when s1 => r<=’0’; a<=’1’; v<=’0’; dec <= “0000”;
if cuenta = 9999 then end …..; if contador = 2 then elsif rising_edge(x) then
cuenta <= (others =>’0’); es <= s2; uni <= uni + 1;
z = 1; Mostrar 2 Letras, Frec 50m A 100 else es <= s1; end if; if uni = 9 then
end if; entity ….. is when s2 => r<=’1’; a<=’0’; v<=’0’; uni <= “0000”;
if e1=’0’ and e0=’0’ then port(clk: in std_logic; if contador = 22 then dec <= dec + 1;
z <=’0’; buzzer: out std_logic; es <= s0; if dec = 9 then
elsif e1=’0’ and e0=’1’ then disply, ena: out std_logic_vector else es <= s2; end if; dec = “0000”;
if cuenta < 1500 then (7 dt 0)); end case; end if;
z <= ‘1’; end ……; end process; end if;
else architecture …… of ….. is rojo<=r when contador < 17 else end if;
z <= ‘0’; signal x: std_logic; clk; end process;
elsif e1=’1’ and e0=’0’ then signal cuenta: std_logic_vector end …….; buzzer <= ‘1’;
if cuenta < 8500 then (17 dt 0); Salidas Sel=1(Gray), Sel=0(Exceso 3) end …….;
z <= ‘1’; begin entity ……. is Letra “S” En Matriz Led 7x5
else buzzer <= ‘1’; port (clk, sel: in std_logic; entity …… is
z <= ‘0’ display <= “10010010” when x=’0’ d: in std_logic_vector (3 dt 0); port (clk: in std_logic;
elsif e1=’1’ and e0=’1’ then else “11000110”; q: buffer std_logic_vector buzzer: out std_logic;
if cuenta < 1500 then ena <= “11111110” when x=’0’ else (3 dt 0)); fil, col: out std_logic_vector
z <= ‘1’; “11111101”; end …….; (4 dt 0);
else process(clk) architectura ……. of ……. is end ………..;
z <= ‘0’ begin begin architecture ….. of …… is
end if; if rising_edge(clk) then process (clk) signal x: std_logic_vector (2 dt 0);
end if; cuenta <= cuenta + 1; begin signal cuenta: std_logic_vector
end if; if cuneta = 250000 then if rising_edge(clk) then (15 downto 0);
end process; cuenta <= (others=>’0’); if sel = ‘1’ then begin
end solucion; x <= notx; q(3) <= d(3); wth x selct fil<=“11110”whn“000”,
Display Asc/Des(0 A 7) Frec 50m A 1 end if; q(2) <= d(3) xor d(2); “0110110” when “001”|”010”|”011”,
entity ……. is end if; q(1) <= d(2) xor d(1); “1001101” when others;
port(clk, ud: in std_logic; end process; q(0) <= d(1) xor d(0);
display: out std_logic_vector end …………; else wth x selct col<=“11110”whn“000”
(7 downto 0)); Semaforo q <= d + 3; “11101” when “001”,
end ……….; entity ……. is end if; “11011” when “010”,
architecture …. of …… is port(clk, stop : in std_logic; end if; “10111” when “011”,
signal x: std_logic; r,a,v: out std_logic); end process; “01111” when others;
signal y: std_logic_vector(2 dt 0); end …… ; end ………. ; process (clk)
signal cuenta: std_logic_vector (24 dt 0); architecture ….. of ….. is Contador Bcd 0 A 99 begin
begin signl contador: std_logic_vector entity …… is if rising_edge (clk) then
u2: process(x) (4 dt 0); port (clk, clr: in std_logic; cuenta <= cuenta + 1;
begin type estados is (s0, s1, s2); buzzer: out std_logic; if cuenta = 250000 then
if risin_edge(x) then signal ep, es: estados; uni, dec: buffer std_logic_vector cuenta <= (others =>’0’);
if ud=’0’ then signal rojo: std_logic; (3 dt 0)); x <= x + 1;
y <= y + 1; begin end ………; if x = 4 then
else process (clk) architecture ……. of …… is x <= (others =>’0’);
y <= y – 1; begin signal x: std_logic; end if;
end if; if rising_edge(clk) then signal cuenta: std_logic_vector end if;
end if; ep <= es; (24 dt 0); end if;
end process u2; case ep is begin end process;
u3: with y select display <= when s0 =>contador<=“00000”; process (clk) buzzer <= ‘1’;
“11000000” when “000”; when others=>contador<= begin end ……..;
Detector De 10110 "11111101" when cont ="01" else then c0<= "10100100"; signal temp: std_logic_vector (4 dt 0);
entity …… "11111011"; elsif s0 = "0011" begin
port (d, clk: in std_logic; process(clk) then c0<= "10110000"; temp <= ‘0’ & d when d < 10 else
q: out std_logic); begin elsif s0="0100" “10000” when d = 10 else
end ………; if rising_edge(clk) then then c0 <= "10011001"; “10001” when d = 11 else
architecture ….. of …….. is cuentita <= cuentita+1; elsif s0="0101" “10010” when d = 12 else
type estados is (s0,s1,s2,s3,s4,s5); if cuentita = 25000000 then then c0<= "10010010"; “10011” when d = 13 else
signal ep, es: estados; cuentita <= (others => '0'); elsif s0="0110" “10100” when d = 14 else “10101”;
begin x<=not x; then c0<="10000010"; bcd <= temp (4);
process (clk) end if; elsif s0="0111" bcd <= temp(3 downto 0);
begin end if; then c0<="11111000"; end …….;
if rising_edge(clk) then end process; elsif s0="1000" Detector De Paridad Impar D #8bit
ep <= es; process(clk) then c0<="10000000"; entity …….. is
end if; begin elsif s0="1001" port (d: in std_logic_vector
end process; if rising_edge(clk) then then c0<="10011000"; (7 dt 0);
process (ep, d) cuenteo<=cuenteo+1; end if; z: out std_logic);
begin if cuenteo=50000 then elsif cont="01" then if s1 = "0000" end ……..;
es <= ep; cuenteo<=(others=>'0'); then c0<= "11000000"; architecture …… of …… is
case ep is l<=not l; elsif s1 = "0001" begin
when s0 => q <= ‘0’; end if; then c0<= "11111001"; z <= d(7) xor d(6) xor
if d = ‘1’ then end if; elsif s1 = "0010" d(5) xor d(4) xor
es <= s1; end process; then c0<= "10100100"; d(3) xor d(2) xor
else es <= s0; end if; process(x,reset,stop,start) elsif s1 = "0011" d(1) xor d(0);
when s1 => q <= ‘0’; begin then c0<= "10110000"; end ……. ;
if d = ‘1’ then if reset='0' then elsif s1="0100" Generador De Secuencias
es <= s1; s0<="0000"; then c0 <= "10011001";
entity …….. is
else es <= s2; end if; s1<="0000"; elsif s1="0101"
port ( clk: in std_logic;
when s2 => q <= ‘0’; min<="0000"; then c0<= "10010010";
z: out std_logic);
if d = ‘1’ then elsif start='0' then end if;
end ……;
es <= s3; if rising_edge(x) then elsif cont="10" then if min = "0000"
architecture …. of …. is
else es <= s0; end if; s0<=s0+'1'; then c0<= "11000000";
signal contador: integer range 0 to 19;
………………….. if s0="1001" then elsif min = "0001"
begin
when s5 => q <= ‘1’; s0<="0000"; then c0<= "11111001";
with contador select z <= ‘1’ when 0|5|6|10|11|12|15|16|17|
if d = ‘1’ then s1<=s1+'1'; elsif min = "0010"
18, ‘0’ when others;
es <= s4; if s1="0101" then then c0<= "10100100";
process (clk)
else es <= s2; end if; s1<="0000"; elsif min = "0011"
begin
end case; min<=min+'1'; then c0<= "10110000";
if falling_edge(clk) then
end process; if min="1001" then elsif min="0100"
contador <= contador + 1;
end ……; min<="0000"; then c0 <= "10011001";
if contador = 19 then
Display Minutos Y Segundos end if; elsif min="0101"
contador <= 0;
end if; then c0<= "10010010";
entity …….. is end if;
end if; elsif min="0110"
port(clk, reset,start,stop: in end if;
elsif stop='0' then then c0<="10000010";
std_logic; end process;
s0<=s0; elsif min="0111"
enable: out std_logic_vector end …..;
s1<=s1; then c0<="11111000";
(7 downto 0); Salida Paradea Al Pulsar Boton
min<=min; elsif min="1000"
buzz: out std_logic; entity …… is
end if; then c0<="10000000";
c0: out std_logic_vector port(clk, boton: in std_logic;
end if; elsif min="1001"
(7 downto 0)); z: out std_logic);
end process; then c0<="10011000";
end …………; end…..;
process (l) end if;
architecture sol of minutosegundo is architecture …… of ….. is
begin end if;
signal x, l: std_logic; signal q: std_logic;
if rising_edge (l) then end process;
signal cuentita: std_logic_vector begin
cont<=cont+'1'; buzz<='1';
(24 downto 0); process(boton)
if cont="10" then end sol;
signal min,s1,s0,z: std_logic_vectr begin
cont<="00"; Conversor Binario A Bcd (4 Bits)
(3 downto 0); if falling_edge(boton) then
end if; entity ……. is
signal cont: std_logic_vector q <= not q; end if; end process;
end if; port ( d: in std_logic_vector
(1 downto 0); z <= clk when q = ‘1’ else ‘0’;
if cont ="00" then if s0 = "0000" (3 dt 0);
signal cuenteo: std_logic_vector end;
then c0 <= "11000000"; bcd1: out std_logic;
(15 downto 0); elsif s0 = "0001" bcd0: out logic_vector (3 dt 0));
begin then c0 <= "11111001"; end …….;
enable <= "11111110" when cont = elsif s0 = "0010" architecture ….. of ….. is
"00" else
Para Una Secuencia: 10110 cont1<=cont1+1; begin “11111001” when “others”;
entity secuencia is if cont1=50000000 then if rising_edge(clk) then end sol;
port (d, clk: in std_logic; cont1<=(others=>´0´); ep<=es; Contador_max2 con divisor y deco7.
q: out std_logic); p<=notp; end if; entity cont_max2 is
end secuencia; end if; end process; port(clk: in std_logic;
architecture sol of secuencia is end if; process(ep) buzzer: out std_logic;
type estados is (s0, s1, s2, s3, s4, s5); end process; begin display: out std_logic_vector(7 downto 0);
signal ep, es: estados; process(clk) es<=ep; habilitador: out std_logic_vector(7 downto 0));
begin variable cont2: std_logic_vector (19 downto 0); case ep is end cont_max2;
process(clk) begin when y0=>a<=´0´; b<=´0´; architecture sol of cont_max2 is
begin if p=0 then componet divisor_1hz;
if rising_edge(clk) then h(0)<=”1100011”; port(clk: in std_logic;
when y1=>a<=´0´; b<=´1´;
ep<=es; h(1)<=”1000010”; z: buzzer std_logic);
end if; h(2)<=”1100111”; end component;
when y2=>a<=´1´; b<=´0´;
end process; h(3)<=”1100111”; component deco7;
process(ep, d) else port(entrada: in std_logic_ vector (3 downto 0));
when y3=>a<=´1´; b<=´1´;
begin h(0)<=”0110111”; display: out std_logic_vector (7 downto 0);
es<=ep; h(1)<=”1111110”; end component;
end case;
case ep is h(2)<=”1000010”; signal x: std_logic;
end process;
when s0=>q<=´0´; h(3)<=”1101101”; signal y: std_logic_vector(3 downto 0);
end solución;
if d=´1´ then es<=s1; endif; begin
else es<=s0; if clk=´1´ and clk´event then ch: divisor_1hz port map(clk,x);
Divisor 5mhz A 1hz
end if; cont2<= cont2+1; k: deco7 port map (y,display);
entity div_1hz is
when s1=>q<=´0´; if cont2<250000 then habilitador<=”01111111”;
port(clk: in std_logic;
if d=´1´ then es<=s1; display<=h(0); buzzer<=´1´;
z: buffer std_logic);
else es<=s2; selec<=”1000”; process(x)
end div_1hz;
end if; elsif cont2<500000 then begin
architecture sol of div_1hz is
when s2=>q<=´0´; display<=h(1); if rising_edge(x) then
signal cuenta: std_logic_vector(25 downto 0);
if d=´1´ then es<=s3; selec<=”0100”; y<=y+1;
begin
else es<=s0; elsif cont2<750000 then end if;
process(clk)
end if; display<=h(2); end process;
begin
when s3=>q<=´0´; selec<=”0010”; end sol;
if rising_edge(clk) then
if d=´1´ then es<=s4; elsif cont2<1000000 then Implementa la sig. Cadena de bits 10011001. Cada bit
cuenta<=cuenta+1;
else es<=s2; display<=h(3); dura 100ms. La transmision pasa cuando presiona load.
if cuenta=25000000 then;
end if; selec<=”0001”; para 100ms es 10hz y en 50mhz tenemos 5000000 pulsos
cuenta<=(others=>´0´);
when s4=>q<=´0´; elsif cont2<1000000 then entity cadena is
z<=not z;
if d=´1´ then es<=s1; cont2<=(others=>´0´); port(load: in std_logic;
end if;
else es<=s5; end if; clk: in std_logic;
end if;
end if; end if; z: out std_logic);
end process;
when s5=>q<=´1´; end process; end cadena;
end sol;
if d=´1´ then es<=s3; end sol; architecture sol of cadena is
Habilitador de display:
else es<=s0; Seguidor de línea, s1 y s2 sensores(zona blanca(1) negra begin
entity deco7 is;
end if; (0)). A y b motor(avanza(1) para(0)) process(clk, load)
port(entrada: in std_logic_vector (3 downto 0));
end case; entity prob2 is variable cont1: std_logic_vector (48 downto 0);
display: out std_logic_vector (7 downto 0);
end if; port (s1,s2, clk: in std_logic;
end deco7; if s1=´0´and s2=´0´ then
end process; a,b: out std_logic);
architecture sol of deco7 is es<=y3;
end solución; end prob2;
begin else
En una matriz 4 display a 7 seg. Muestre fiee 1seg y 2015
with entrada select display<= if s1=´0´and s2=´1´ then
1seg. Repetir la secuencia:
“11111001” when “0001”, es<=y1;
entity fiee-20215 is
“10100100” when “0010”, else
port(type: h array (3 to 0): std_logic_vector(6 downto 0));
“11111001” when “0011”, if s1=´1´and s2=´0´ then
clk: in std_logic;
“11111001” when “0100”, es<=y2;
selec: out std_logic_vector(3 downto 0);
“11111001” when “0101”, end if; (x3)
display: out std_logic_vector (6 downto 0);
“11111001” when “0110”,
end fiee-2015; variable cont2: std_logic_vector (2 downto 0);
“11111001” when “0111”,
architecture sol of fiee-2015 is begin
“11111001” when “1000”,
begin arc if load=´0´ then
“11111001” when “1001”,
process(clk) hitecture sol of prob2 is z<=´0´;
“11111001” when “1010”,
variable cont1: std_logic_ vector (25 downto 0); type estados is (y0,y1,y2,y3); elsif clk=´1´ and clk´event then
“11111001” when “1011”,
p: std_logic; signal ep, es: estados; cont1<=cont1+1;
“11111001” when “1100”,
begin begin if cont1=5000000 then
“11111001” when “1101”,
if clk=´1´and clk´event then process(clk) cont2<=cont2+1;
“11111001” when “1110”,
 cont1<=(others=>´0´); 3. implemente un convertidor de binario de 4 bits a
if cont2=0 then código gray.
z<=´1´;
elsif cont2<3 then
z<=´0´;
elsif cont2<5 then
z<=´1´;
elsif cont2<7 then
z<=´0´;
elsif z<=´1´;
end if; (x3)
end process;
end sol;
1. implementar un sumador de dos números de 4 bits a y
b con acarreo de entrada, cuya salida tenga:magnitud de
4 bits,acarreo de salida. .Implem
ente un circuito demultiplexor de 3 a 8 con habilitador.

6. Implemente un codificador BCD (de 0 a 9) a binario(4

bits), debe tener una salida DV (Dato válido) adicional
que indique que se está activando una entrada. Nota, si
se activan más de una entrada, se debe codificar el de
mayor magnitud)

2.implementar un multiplicador de dos números de 8 bits

c/u (a y b), la salida debe mostrar el mayor resultado que
se puede realizar con estos dos números.
. Implemente un sumador de dos dígitos en BCD

5. Implemente un circuito que detecte si un número

ingresado (de 4 bits) es múltiplo de 3.