Device Terprogram-

Finite State Machine

Oleh: Misbah, ST, MT
Program Studi Teknik Elektro-UMG
Finite state machine (FSM)
• Mealy FSM : Output tidak hanya bergantung pada present state tapi
juga input.

OL
x y y z
NS D- FF
Mealy FSM
qq=state
z = output
x = input qq
00
 = transisi
1/1 x/z
0/1 1/1

10 0/0
01 x/z
0/1 1/0
FSM (2)
• Moore FSM : Output hanya tergantung pada present state.

OL z
x NS y D- FF y
Moore FSM
qq = state
zz = output
x = input
 = transisi qq/
zz00/01

X=1
x=1
x=0

10/11 X=0
01/11 X=0
x=1
library ieee;
use ieee.std_logic_1164.all;

entity mealy1 is port( when state3 =>

clk, rst: in std_logic; if id < x"7" then
id: in std_logic_vector(3 downto 0); state <= state0;
w: out std_logic; elsif id = x"9" then
y: out std_logic_vector(1 downto 0)); state <= state4;
end mealy1; else
state <= state3;
architecture archmealy1 of mealy1 is end if;
type states is (state0, state1, state2, state3, state4); when state4 =>
signal state: states; if id = x"b" then
Begin state <= state0;
process (clk, rst) Else
begin state <= state4;
if rst='1' then end if;
state <= state0; end case;
elsif (clk'event and clk='1') then end if;
case state is end process;
when state0 =>
if id = x"3" then --assign moore state outputs;
state <= state1; y <= "00" when (state=state0) else
else "10" when (state=state1 or state=state3) else
state <= state0; "11";
end if; --assign mealy output;
when state1 => w <= '0' when (state=state3 and id < x"7") else
state <= state2; '1';
when state2 => end archmealy1;
if id = x"7" then
state <= state3;
Else
state <= state2;
end if;
Motor Stepper
Driver Motor Stepper ( full step )
Step L1 L2 L3 L4 Step L1 L2 L3 L4
1 1 0 0 1 1 1 0 0 1

2 1 1 0 0 2 0 0 1 1

3 0 1 1 0 3 0 1 1 0

4 0 0 1 1 4 1 1 0 0

Searah Jarum Jam Berlawanan Jarum Jam

Diagram State Driver Motor Stepper (Moore)
• D : Direction 00/
1001
D=‘1’
• L1,L2,L3,L4 : output D=‘1’
(1001,1100,0110,001 D=‘0’
D=‘0’
1) 11/
0011 01/
1100
• State : 00,01,10,11
D=‘0’ D=‘0’

D=‘1’ D=‘1’
10/
0110
WARP 6.3 Active FSM
Lanjutan ...
• Pada clk properti dibuat seperti • Pada Menu FSM  Machine 
pd gambar. Sreg0
library IEEE;
use IEEE.std_logic_1164.all;
entity fsm1 is when S3 =>
port (clk: in STD_LOGIC; if D='1' then
D: in STD_LOGIC; Sreg0 <= S4;
L: out STD_LOGIC_VECTOR (3 downto 0)); elsif D='0' then
end; Sreg0 <= S2;
architecture fsm1_arch of fsm1 is end if;
-- SYMBOLIC ENCODED state machine: Sreg0 when S4 =>
type Sreg0_type is (S1, S2, S3, S4); if D='1' then
signal Sreg0: Sreg0_type; Sreg0 <= S1;
begin elsif D='0' then
--concurrent signal assignments Sreg0 <= S3;
--diagram ACTIONS; end if;
Sreg0_machine: process (clk) when others =>
Begin null;
if clk'event and clk = '1' then end case;
case Sreg0 is end if;
when S1 => end process;
if D='0' then
Sreg0 <= S4; -- signal assignment statements
elsif D='1' then -- for combinatorial outputs
Sreg0 <= S2; L_assignment:
end if; L <= "1001" when (Sreg0 = S1) else
when S2 => "1100" when (Sreg0 = S2) else
if D=1 then "0110" when (Sreg0 = S3) else
Sreg0 <= S3; "0011" when (Sreg0 = S4) else
elsif D='0' then "0011";
Sreg0 <= S1;
end if; end fsm1_arch;
Tugas:
• Buatlah tampilan 8 huruf dari belakang Nama Anda dengan
menggunakan FSM!