Cheka Curativo ECE 127 Homework 3

Problem 1: Designing an FSM

Consider the design of a Moore-style FSM with a 1-bit input (x), and a 1-bit output (y). The FSM accepts
inputs one bit at a time and outputs a 0 until it sees the sequence 0101 (with no other bit values in
between). After seeing the second 1 in the sequence it outputs a 1 and then starts over.

(a) Draw the state transition diagram. Label all nodes and arcs.

x=1 x=1

x=0
Waiting First Second
Y=0 x=0 Y=0 x=1 Y=0

x=0 x=0

Fourth x=1 Third

Y=1 Y=0

x=0

(b) Derive the next state logic and the output logic equations.
One way is to use one-hot encoding and 5 bits to express states:

SWAITING = 00001
SFIRST = 00010
SSECOND = 00100
STHIRD = 01000
SFOURTH = 10000

Then each of the 5 bits of the next state (n) are derived from the current state c and
input x as follows, also assuming that there is a reset r:

y = c4
n0 = r + c1x + c2x + c3x + c4x + c0
= r + x(c2 + c4 + c0) + x (c1 + c3)
n1 = r c0x
n2 = r c1x
n3 = r c2x
n4 = r c3x
Problem 2: Implementing an FSM
Consider the state transition diagram shown below:

(a) Write the Verilog behavior description for the corresponding circuit.
module Problem(clk, rst, in, out); if (in == 1'b1) next_state = S3;
input clk, rst; else next_state = S2;
input in; end
output out; S2: begin
parameter S0 = 2'b00; out = 1'b1;
parameter S1 = 2'b01; if (in == 1'b1) next_state = S2;
parameter S2 = 2'b10; else next_state = S0;
parameter S3 = 2'b11; end
reg out; S3: begin
reg [1:0] present_state, next_state; out = 1'b0;
always @(posedge clk) if (in == 1'b1) next_state = S2;
if (rst) present_state <= S0; else next_state = S0;
else present_state <= next_state; end
always @(present_state or in) // No 'default' case needed.
case (present_state) endcase
S0: begin endmodule
out = 1'b0;

if (in == 1'b1) next_state = S1;

else next_state = S3;
end
S1: begin
out = 1'b1;
 (b) Draw the circuit diagram for one-hot encoded implementation. (You may assume that flip-flops
have both "set" and "reset" inputs, but you must label which one you would use for each flip-
flop.)

Problem 3: Converting from Mealy to Moore Style

Convert the Mealy-style state transition diagram to a Moore-style.

Answer:
1

SO 1
0

0
0
A
SO SO
A
0 0 0
A
1
0

1
SO
0
Problem 4: Verilog Code for a Vending Machine
The State Diagram of the Vending Machine is given here. It has the following states:
State 1: Reset
State 2: Five
State 3: Ten
State 4: Fifteen
State 5: Twenty
State 6: Twenty Five
The next state is the RESET state again. The diagram is given below and is self-explanatory.
Whenever a coin is dropped, the system jumps to the next state. For example, if the coin dropped from
the RESET State is a NICKEL, then the system jumps to the FIVE State. Otherwise, the system stays in
the
present state. When the system gets an extra amount, it goes back to the RESET State and the difference
is given back to the user. Write the Verilog behavior description of this vending machine system.
Answer:
\\module name default: next_state=IDLE;
module fsm(clock,reset,coin,vend,state,change); endcase
\\these are the inputs and the outputs. FIVE: case(coin) \\THIS IS THE SECOND
input clock; STATE
input reset; 7
input [2:0]coin; NICKEL: next_state=TEN;
output vend; DIME: next_state=FIFTEEN;
output [2:0]state; QUARTER: next_state=TWENTYFIVE;
output [2:0]change; //change=NICKEL
6 default: next_state=FIVE;
\\i need to define the registers as change,coin endcase
and vend TEN: case(coin) \\THIS IS THE THIRD STATE
reg vend; NICKEL: next_state=FIFTEEN;
reg [2:0]change; DIME: next_state=TWENTY;
wire [2:0]coin; QUARTER: next_state=TWENTYFIVE;
\\my coins are declared as parameters to make //change=DIME
reading better. default: next_state=TEN;
parameter [2:0]NICKEL=3’b001; endcase
parameter [2:0]DIME=3’b010; FIFTEEN: case(coin) \\THIS IS THE FOURTH
parameter [2:0]NICKEL_DIME=3’b011; STATE
parameter [2:0]DIME_DIME=3’b100; NICKEL: next_state=TWENTY;
parameter [2:0]QUARTER=3’b101; DIME: next_state=TWENTYFIVE;
\\MY STATES ARE ALSO PARAMETERS . I QUARTER: next_state=TWENTYFIVE;
DONT WANT TO MAKE YOU READ //change==NICKEL_DIME
\\IN MACHINE LANGUAGE default: next_state=FIFTEEN;
parameter [2:0]IDLE=3’b000; endcase
parameter [2:0]FIVE=3’b001; TWENTY: case(coin) \\THIS IS THE FIFTH
parameter [2:0]TEN=3’b010; STATE
parameter [2:0]FIFTEEN=3’b011; NICKEL: next_state=TWENTYFIVE;
parameter [2:0]TWENTY=3’b100; DIME: next_state=TWENTYFIVE;
parameter [2:0]TWENTYFIVE=3’b101; //change=NICKEL
\\AS ALWAYS THE STATES ARE DEFINED QUARTER: next_state=TWENTYFIVE;
AS REG //change==DIME_DIME
reg [2:0]state,next_state; default: next_state=TWENTY;
\\MY MACHINE WORKS ON STATE AND endcase
COIN TWENTYFIVE: next_state=IDLE; \\THE
always @(state or coin) NEXT STATE HERE IS THE RESET
begin default : next_state=IDLE;
next_state=0; \\VERYFIRST NEXT STATE IS endcase
GIVEN ZERO end
case(state) always @(clock)
IDLE: case(coin) \\THIS IS THE IDLE STATE begin \\WHENEVER I GIVE A RESET I
NICKEL: next_state=FIVE; HAVE TO MAKE THE STATE TO IDLE AND
DIME: next_state=TEN; VEND TO 1
QUARTER: next_state=TWENTYFIVE; if(reset) begin
state <= IDLE;
vend <= 1’b0;
// change <= 3’b000;
end \\THE CHANGE ALSO HAS TO
BECOME NONE
else state <= next_state;
8
case (state) \\HERE WE DECIDE THE NEXT
STATE
\\ALL THE STATES ARE DEFINED HERE
AND THE OUTPUT IS ALSO GIVEN
IDLE: begin vend <= 1’b0; change <=3’d0; end
FIVE: begin vend <= 1’b0; if
(coin==QUARTER) change <=NICKEL; else
change <=3’d0; end
TEN: begin vend <= 1’b0; if
(coin==QUARTER) change <=DIME; else
change <= 3’d0; end
FIFTEEN : begin vend <= 1’b0; if
(coin==QUARTER) change
<=NICKEL_DIME; else change <= 3’d0; end
TWENTY : begin vend <= 1’b0; if
(coin==DIME) change <=NICKEL; else if
(coin==QUARTER) change <=DIME_DIME;
else change <= 3’d0; end
TWENTYFIVE : begin vend <= 1’b1; change
<=3’d0; end
default: state <= IDLE;
endcase
end
endmodule