VENDING MACHINE CONTROLLER

Here we have designed controller for vending machine, which

sells candy for 30 cents. Finite state machine (FSM) constitute a
special modelling technique for sequential logic circuits. Such a
model can be very useful in design of certain types of system,
particularly those whose tasks form a well define sequence.
The inputs and outputs of controller are shown in figure 2. The
input signals are nickel_in, dime_in and quarter_in indicates that
corresponding coin has been deposited. Two additional input
clk(clock) and rst(reset) are also necessary. The controller responds
with 3 output: candy_out,to despense a candy bar, plus nickel_out and
dime_out, asserted when change is due.
Figure 3 shows the states of corresponding FSM. The number inside
the circle represent total amount deposited by the customer(only
nickel,dime and quarter are accepted) . state 0 is the idle state. From it
if nickel is deposited machine moves to the state 5,if dime is
deposited it moves to state 10,if quarter is deposited it moves to state
25. If state 30 is reached then a candy is dispensed, with no change. If
state 40 is reached then a nickel is delivered and candy is dispensed.
The three states are marked with circles are those from which a candy
bar is delivered and machine returns to the zero state.
FIGURE 1

FIGURE 2
FIGURE 3
VHDL CODE

library ieee;

use ieee.std_logic_1164.all;

entity vending_machine is

port(NICKEL_IN, DIME_IN, QUARTER_IN:IN BOOLEAN;

CLK,RST:IN std_logic;

NICKEL_OUT, DIME_OUT, CANDY_OUT: out std_logic);

End vending_machine;

architecture fsm of vending_machine is

type STATE is (st0, st5, st10, st15, st20, st25, st30, st35,st40, st45,st50);

signal present_STATE, NEXT_STATE: STATE;

begin

process (rst,clk)

begin

if (rst='1') then

present_state <= st0;

elsif(clk'event and clk='1') then

present_state <= next_state;

end if;
end process;

process (NICKEL_IN, DIME_IN, QUARTER_IN,PRESENT_STATE)

begin

case present_state is

when st0 =>

candy_out <= '0';

nickel_out <= '0';

dime_out <= '0';

if(NICKEL_IN) then NEXT_STATE <= st5;

elsif(DIME_IN) then NEXT_STATE <= st10;

elsif(QUARTER_IN) then NEXT_STATE <= st25;

else next_state <= st0;

end if;

when st5 =>

candy_out <= '0';

nickel_out <= '0';

dime_out <= '0';

if(NICKEL_IN) then NEXT_STATE <= st10;

elsif(DIME_IN) then NEXT_STATE <= st15;

elsif(QUARTER_IN) then NEXT_STATE <= st30;

else next_state <= st5;

end if;

when st10 =>

candy_out <= '0';

nickel_out <= '0';

dime_out <= '0';

if(NICKEL_IN) then NEXT_STATE <= st15;

elsif(DIME_IN) then NEXT_STATE <= st20;

elsif(QUARTER_IN) then NEXT_STATE <= st35;

else next_state <= st10;

end if;

when st15 =>

candy_out <= '0';

nickel_out <= '0';

dime_out <= '0';

if(NICKEL_IN) then NEXT_STATE <= st20;

elsif(DIME_IN) then NEXT_STATE <= st25;

elsif(QUARTER_IN) then NEXT_STATE <= st40;

else next_state <= st15;

end if;

when st20 =>

candy_out <= '0';

nickel_out <= '0';

dime_out <= '0';

if(NICKEL_IN) then NEXT_STATE <= st25;

elsif(DIME_IN) then NEXT_STATE <= st30;

elsif(QUARTER_IN) then NEXT_STATE <= st45;

else next_state <= st20;

end if;

when st25 =>

candy_out <= '0';

nickel_out <= '0';

dime_out <= '0';

next_state <= st0;

if(NICKEL_IN) then NEXT_STATE <= st30;

elsif(DIME_IN) then NEXT_STATE <= st35;

elsif(QUARTER_IN) then NEXT_STATE <= st50;

else next_state <= st25;

end if;
when st30 =>

candy_out <= '1';

nickel_out <= '0';

dime_out <= '0';

next_state <= st0;

when st35 =>

candy_out <= '1';

nickel_out <= '1';

dime_out <= '0';

next_state <= st0;

when st40 =>

candy_out <= '1';

nickel_out <= '0';

dime_out <= '1';

next_state <= st0;

when st45 =>

candy_out <= '0';

nickel_out <= '0';

dime_out <= '1';

next_state <= st35;

when st50 =>

candy_out <= '0';

nickel_out <= '0';

dime_out <= '1';

next_state <= st40;

end case;

end process;

end fsm;

Vector waveform