UNIVERSIDADE FEDERAL DO ESPÍRITO SANTO

CENTRO TECNOLÓGICO – Departamento de Engenharia Elétrica

Circuitos Lógicos – Lista para a PLab2
Data: 01/12/2023
Aluno 1: _______________________________________________Turma Lab. :___
Aluno 2: _______________________________________________Turma Lab. :___

1) Observe o circuito descrito em VHDL abaixo. Este circuito é combinacional e tem duas arquiteturas que realizam exatamente a
mesma função. a) Desenhe o circuito que é criado em cada uma das arquiteturas. b) Explique o que o circuito realiza.
library ieee;
use ieee.std_logic_1164.all; architecture multi_stage_arch of barrel_shifter is
entity barrel_shifter is signal s0, s1: std_logic_vector(7 downto 0);
port( begin
a: in std_logic_vector(7 downto 0); -- stage 0
amt: in std_logic_vector(2 downto 0); s0 <= a(0) & a(7 downto 1) when amt(0)='1'
y: out std_logic_vector(7 downto 0) else a;
); -- stage 1
end barrel_shifter; s1 <= s0(1 downto 0) & s0(7 downto 2) when amt(1)='1'
else s0;
architecture sel_arch of barrel_shifter is -- stage 2
begin y <= s1(3 downto 0) & s1(7 downto 4) when amt(2)='1'
with amt select else s1;
y<= a when "000", end multi_stage_arch;
a(0) & a(7 downto 1) when "001",
a(1 downto 0) & a(7 downto 2) when "010",
a(2 downto 0) & a(7 downto 3) when "011",
a(3 downto 0) & a(7 downto 4) when "100",
a(4 downto 0) & a(7 downto 5) when "101",
a(5 downto 0) & a(7 downto 6) when "110",
a(6 downto 0) & a(7) when others; -- 111
end sel_arch;

2) Desenhe o grafo da máquina de estados descrita em VHDL abaixo. Atenção que a máquina tem saída Mealy e Moore.
library ieee; when read2 =>
use ieee.std_logic_1164.all; state_next <= read3;
entity mem_ctrl is when read3 =>
port( state_next <= read4;
clk, reset: in std_logic; when read4 =>
mem, rw, burst: in std_logic; state_next <= idle;
oe, we, we_me: out std_logic end case;
); end process;
end mem_ctrl ; -- Moore output logic
process(state_reg)
architecture mult_seg_arch of mem_ctrl is begin
type mc_state_type is (idle, read1, read2, read3, we <= '0'; -- default value
read4, write); oe <= '0'; -- default value
signal state_reg, state_next: mc_state_type; case state_reg is
begin when idle =>
-- state register when write =>
process(clk,reset) we <= '1';
begin when read1 =>
if (reset='1') then oe <= '1';
state_reg <= idle; when read2 =>
elsif (clk'event and clk='1') then oe <= '1';
state_reg <= state_next; when read3 =>
end if; oe <= '1';
end process; when read4 =>
-- next-state logic oe <= '1';
process(state_reg,mem,rw,burst) end case;
begin end process;
case state_reg is -- Mealy output logic
when idle => process(state_reg,mem,rw)
if mem='1' then begin
if rw='1' then we_me <= '0'; -- default value
state_next <= read1; case state_reg is
else when idle =>
state_next <= write; if (mem='1') and (rw='0') then
end if; we_me <= '1';
else end if;
state_next <= idle; when write =>
end if; when read1 =>
when write => when read2 =>
state_next <= idle; when read3 =>
when read1 => when read4 =>
if (burst='1') then end case;
state_next <= read2; end process;
else end mult_seg_arch;
state_next <= idle;
end if;
3) Observe o circuito descrito em VHDL abaixo.
library ieee; when q2=> if x = '0' then
use iee.std_logic_1164.all; state_next <= q4;
entity maq1 is else
port( clk: in std_logic; state_next <= q3;
rst: in std_logic; end if;
x: in std_logic; when q3=> if x = '0' then
z1,z0: out std_logic); state_next <= q4;
end maq1; end if;
when q4=> if x = '0' then
architecture behavioral of maq1 is state_next <= q1;
type state_type is (q0,q1,q2,q3,q4); else
signal state_reg, state_next: state_type; state_next <= q2;
begin end if;
process(clk, rst) end case;
begin end if;
if rst = '1' then end process;
state_reg <= q0; process(state_reg, x)
elsif clk’event and clk = '1' then begin
state_reg <= state_next; case state_reg is
end if; when q2 => z1 <= x;
end process; z0 <= '0';
process(state_reg, x) when q4 => z1 <= '0';
begin z0 <= x;
state_next <= state_reg; when others => z1 <= '0';
case state_reg is z0 <= '0';
when q0=>if x = '0' then end case;
state_next <= q1; end process;
else end behavioral;
state_next <= q3;
end if;
when q1=>if x = '1' then
state_next <= q2;
end if;

a- Esta é uma máquina de estados Mealy ou Moore? Justifique.

b- Desenhe o grafo da máquina de estados correspondente.

4) Para a descrição de hardware abaixo, desenhe completamente o circuito digital que se pode inferir. Diga qual a função deste circuito,
explicando-a.

library ieee; library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
entity circ1 is entity circ3 is
port (a1,a0: in std_logic; port(clk: in std_logic;
c: in std_logic; rst: in std_logic;
s: out std_logic); x: in std_logic_vector(3 downto 0);
end circ1; ld: in std_logic;
architecture behavioral of circ1 is z: out std_logic_vector(3 downto 0));
begin end circ3;
s <= a1 when c = '1' else architecture structural of circ3 is
a0; signal r_reg: std_logic_vector (3 downto 0);
end behavioral; signal r_next: std_logic_vector (3 downto 0);
begin
library ieee; u3: entity work.circ1(behavioral) port map (a1=>x(3),
use ieee.std_logic_1164.all; a0=>r_reg(3), c=>ld, s=>r_next(3));
entity circ2 is u2: entity work.circ1(behavioral) port map (a1=>x(2),
port (clk: in std_logic; a0=>r_reg(2), c=>ld, s=>r_next(2));
rst: in std_logic; u1: entity work.circ1(behavioral) port map ((a1=>x(1),
d: in std_logic; a0=>r_reg(1), c=>ld, s=>r_next(1));
q: out std_logic); u0: entity work.circ1(behavioral) port map ((a1=>x(0),
end circ2; a0=>r_reg(0), c=>ld, s=>r_next(0));
architecture behavioral of circ2 is k3: entity work.circ2(behavioral) port map (clk=>clk, rst=>rst,
signal q_reg: std_logic; d=>r_next(3), q=>r_reg(3));
begin k2: entity work.circ2(behavioral) port map (clk=>clk, rst=>rst,
process(clk, rst) d=>r_next(2), q=>r_reg(2));
begin k1: entity work.circ2(behavioral) port map (clk=>clk, rst=>rst,
if rst = '1' then d=>r_next (1), q=>r_reg(1));
q_reg <= '0'; k0: entity work.circ2(behavioral) port map (clk=>clk, rst=>rst,
elsif clk'event and clk = '1' then d=>r_next (0), q=>r_reg(0));
q_reg <= d; z <= r_reg;
end if; end structural;
end process;
q <= q_reg;
end behavioral;
5) Dada a descrição em VHDL abaixo, desenhe completamente o circuito digital. Explique que circuito é este, dizendo seu nome e suas funções.
Atenção que o operador '&' representa concatenação em VHDL.

library ieee; with s select

use ieee.std_logic_1164.all; q_next <= d when "000",
entity p2 is r_in & q_reg(3 downto 1) when "001",
port ( q_reg(2 downto 0) & l_in when "010",
clk, rst: in STD_LOGIC; q_reg(2 downto 0) & q_reg(3) when "011",
r_in, l_in: in STD_LOGIC; q_reg(0) & q_reg(3 downto 1) when "100",
s: in std_logic_vector(2 downto 0); not(q_reg) when "101",
d: in std_logic_vector(3 downto 0); q_reg when others;
z: out std_logic_vector(3 downto 0) z <= q_reg;
); end behavioral;
end p2;
architecture behavioral of p2 is
signal q_reg, q_next: std_logic_vector(3 downto 0);
begin
process (clk, rst)
begin
if (rst='1') then
q_reg <= (others=>'0');
elsif (clk'event and clk='1')then
q_reg <= q_next;
end if;
end process;

Bom trabalho!
Profa. Eliete Caldeira