library ieee ;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity my_ram_interface is
port (
rst_ram : in std_logic;
clk_ram : in std_logic;
ram_en_int : in std_logic;

im_reqn : in std_logic;

ram_data_in : in std_logic_vector(31 downto 0);

wait_processor : out std_logic;

bus_sel : out std_logic;
dd_ins_data : out std_logic_vector(31 downto 0)

);

end my_ram_interface ;

architecture my_ram_interface_a of my_ram_interface is

type state_type is (S0,S1,S2,S3,S4);

signal state_ram : state_type;

signal bus_sel_o : std_logic;

begin

bus_sel <= bus_sel_o after 10 ns;

--
--bus_sel <= bus_sel_o;

ram_p : process (clk_ram,rst_ram,state_ram)

begin

if clk_ram'event and clk_ram = '1' then

if rst_ram = '0' then

wait_processor <= '1';

bus_sel_o <= '0';
state_ram <= S0;
dd_ins_data <= (others => '0');

else
case state_ram is

when S0 =>
 if ram_en_int = '1' then

wait_processor <= '0';

bus_sel_o <= '1';

state_ram <= S1;

end if;

when S1 =>

state_ram <= S2;

when S2 =>

bus_sel_o <= '0';

dd_ins_data <= ram_data_in;

if im_reqn = '0' then

state_ram <= S3; -- ins memory
access
else
state_ram <= S0;
wait_processor <= '1';

end if;

when S3 =>

state_ram <= S4;

when S4 =>

wait_processor <= '1';

state_ram <= S0;

when others =>

null;

end case;

end if;
end if;
end process ram_p;

end my_ram_interface_a;