AUTOMATIC CAR

PARKING SYSTEM
MIS: 7031-7039

Dt. 27/01/2022
Problems:
• Traffic jam
• Security issue
• Wasting time
• Confusing parking policies
• Low parking turnover rate
• Economic loss
-- fpga4student.com FPGA projects, Verilog projects, VHDL projects next_state <= RIGHT_PASS; -- if password is correct, let them in
-- VHDL project: VHDL code for car parking system else
library IEEE; next_state <= WRONG_PASS; -- if not, tell them wrong pass by blinking Green LED
use IEEE.STD_LOGIC_1164.ALL; -- let them input the password again
use IEEE.std_logic_unsigned.all; end if;
entity Car_Parking_System_VHDL is end if;
port when WRONG_PASS =>
( if((password_1="01")and(password_2="10")) then
clk,reset_n: in std_logic; -- clock and reset of the car parking system next_state <= RIGHT_PASS;-- if password is correct, let them in
front_sensor, back_sensor: in std_logic; -- two sensor in front and behind the gate of the car parking system else
password_1, password_2: in std_logic_vector(1 downto 0); -- input password next_state <= WRONG_PASS;-- if not, they cannot get in until the password is right
GREEN_LED,RED_LED: out std_logic; -- signaling LEDs end if; process(clk) -- change this clock to change the LED blinking period
HEX_1, HEX_2: out std_logic_vector(6 downto 0) -- 7-segment Display when RIGHT_PASS => begin
); if(front_sensor='1' and back_sensor = '1') then if(rising_edge(clk)) then
end Car_Parking_System_VHDL; next_state <= STOP; case(current_state) is
-- if the gate is opening for the current car, and the next car come, when IDLE =>
architecture Behavioral of Car_Parking_System_VHDL is -- STOP the next car and require password green_tmp <= '0';
-- FSM States -- the current car going into the car park red_tmp <= '0';
type FSM_States is (IDLE,WAIT_PASSWORD,WRONG_PASS,RIGHT_PASS,STOP); elsif(back_sensor= '1') then HEX_1 <= "1111111"; -- off
signal current_state,next_state: FSM_States; -- if the current car passed the gate an going into the car park HEX_2 <= "1111111"; -- off
signal counter_wait: std_logic_vector(31 downto 0); -- and there is no next car, go to IDLE when WAIT_PASSWORD =>
signal red_tmp, green_tmp: std_logic; next_state <= IDLE; green_tmp <= '0';
else red_tmp <= '1';
begin next_state <= RIGHT_PASS; -- RED LED turn on and Display 7-segment LED as EN to let the car know they need to input
-- Sequential circuits end if; password
process(clk,reset_n) when STOP => HEX_1 <= "0000110"; -- E
begin if((password_1="01")and(password_2="10"))then HEX_2 <= "0101011"; -- n
if(reset_n='0') then -- check password of the next car when WRONG_PASS =>
current_state <= IDLE; -- if the pass is correct, let them in green_tmp <= '0'; -- if password is wrong, RED LED blinking
elsif(rising_edge(clk)) then next_state <= RIGHT_PASS; red_tmp <= not red_tmp;
current_state <= next_state; else HEX_1 <= "0000110"; -- E
end if; next_state <= STOP; HEX_2 <= "0000110"; -- E
end process; end if; when RIGHT_PASS =>
-- combinational logic when others => next_state <= IDLE; green_tmp <= not green_tmp;
-- fpga4student.com FPGA projects, Verilog projects, VHDL projects end case; red_tmp <= '0'; -- if password is correct, GREEN LED blinking
process(current_state,front_sensor,password_1,password_2,back_sensor,counter_wait) end process; HEX_1 <= "0000010"; -- 6
begin -- wait for password HEX_2 <= "1000000"; -- 0
case current_state is process(clk,reset_n) when STOP =>
when IDLE => begin green_tmp <= '0';
if(front_sensor = '1') then -- if the front sensor is on, if(reset_n='0') then red_tmp <= not red_tmp; -- Stop the next car and RED LED blinking
-- there is a car going to the gate counter_wait <= (others => '0'); HEX_1 <= "0010010"; -- 5
next_state <= WAIT_PASSWORD;-- wait for password elsif(rising_edge(clk))then HEX_2 <= "0001100"; -- P
else if(current_state=WAIT_PASSWORD)then when others =>
next_state <= IDLE; counter_wait <= counter_wait + x"00000001"; green_tmp <= '0';
end if; else red_tmp <= '0';
when WAIT_PASSWORD => counter_wait <= (others => '0'); HEX_1 <= "1111111"; -- off
if(counter_wait <= x"00000003") then end if; HEX_2 <= "1111111"; -- off
next_state <= WAIT_PASSWORD; end if; end case;
else -- check password after 4 clock cycles end process; end if;
if((password_1="01")and(password_2="10")) then -- output end process;
RED_LED <= red_tmp ;
GREEN_LED <= green_tmp;
 clk => clk,
reset_n => reset_n,
front_sensor => front_sensor,
-- fpga4student.com FPGA projects, Verilog projects, VHDL projects
back_sensor => back_sensor,
-- VHDL project: VHDL code for car parking system
password_1 => password_1,
-- Testbench code for car parking system in VHDL
password_2 => password_2,
LIBRARY ieee;
GREEN_LED => GREEN_LED,
USE ieee.std_logic_1164.ALL;
RED_LED => RED_LED,
HEX_1 => HEX_1,
ENTITY tb_car_parking_system_VHDL IS
HEX_2 => HEX_2
END tb_car_parking_system_VHDL;
);
ARCHITECTURE behavior OF tb_car_parking_system_VHDL IS
-- Clock process definitions
clk_process :process
-- Component Declaration for the car parking system in VHDL
begin
clk <= '0';
COMPONENT Car_Parking_System_VHDL
wait for clk_period/2;
PORT(
clk <= '1';
clk : IN std_logic;
wait for clk_period/2;
reset_n : IN std_logic;
end process;
front_sensor : IN std_logic;
-- Stimulus process
back_sensor : IN std_logic;
stim_proc: process
password_1 : IN std_logic_vector(1 downto 0);
begin
password_2 : IN std_logic_vector(1 downto 0);
reset_n <= '0';
GREEN_LED : OUT std_logic;
front_sensor <= '0';
RED_LED : OUT std_logic;
back_sensor <= '0';
HEX_1 : OUT std_logic_vector(6 downto 0);
password_1 <= "00";
HEX_2 : OUT std_logic_vector(6 downto 0)
password_2 <= "00";
);
wait for clk_period*10;
END COMPONENT;
reset_n <= '1';
wait for clk_period*10;
front_sensor <= '1';
--Inputs
wait for clk_period*10;
signal clk : std_logic := '0';
password_1 <= "01";
signal reset_n : std_logic := '0';
password_2 <= "10";
signal front_sensor : std_logic := '0';
wait until HEX_1 = "0000010";
signal back_sensor : std_logic := '0';
password_1 <= "00";
signal password_1 : std_logic_vector(1 downto 0) := (others => '0');
password_2 <= "00";
signal password_2 : std_logic_vector(1 downto 0) := (others => '0');
back_sensor <= '1';
wait until HEX_1 = "0010010"; -- stop the next car and require password
--Outputs
password_1 <= "01";
signal GREEN_LED : std_logic;
password_2 <= "10";
signal RED_LED : std_logic;
front_sensor <= '0';
signal HEX_1 : std_logic_vector(6 downto 0);
wait until HEX_1 = "0000010";
signal HEX_2 : std_logic_vector(6 downto 0);
password_1 <= "00";
password_2 <= "00";
-- Clock period definitions
back_sensor <= '1';
constant clk_period : time := 10 ns;
wait until HEX_1 = "1111111";
back_sensor <= '0';
BEGIN
-- insert your stimulus here
-- Instantiate the car parking system in VHDL
wait;
Car_park_system: Car_Parking_System_VHDL PORT MAP (
end process;

END;
Hardware components required:
• Altera
• Sensor
• LED Display
• Power Supply
Conclusion
Recap
• Problems statement
• Methadology
• State diagram
• Vsdl Code
• Hardware component required
•  Its efficiency in alleviating the traffic problem that
arises especially in the city area where traffic
congestion and the insufficient parking spaces are
undeniable. It does so by directing patrons and
optimizing the use of parking spaces.
Thank you