Design of Sequential Circuit using VHDL

VHDL code to detect a bit pattern 1101 in a block of 256 bits

M1:Mod 256 counter

M2:Pattern recognizer

 Detection should restart after each set of 256 bits

Overlapping of bit pattern is allowed

Interconnect M1 and M2

M1: mod 256 counter

VHDL code for counter

architecture behavioral of counter is signal count:integer range 0 to 255; begin process(clk,reset) begin if reset='1' then count<=0; y<='0'; elsif clk='1' and clk'event then if count=255 then count<=0; y<='1'; else count<=count+1; y<='0'; end if; end if; end process; end behavioral;

M2: Pattern recognizer

Interlink between M1 and M2

M1: Mod 256 counter M2: Pattern recognizer

State Diagram of detector

s0

1, 0 / 0

0,1 / 0

01/ 0
1 / 0
s1

01/ 0 01/ 0

0 / 0 11/1

s2

01/1

00/ 0

s3

Code for detector

architecture behavioral of detect is signal state:integer range 0 to 3; begin process (y, x,state,clk) begin if reset='1' then state<=0; z<='0'; elsif clk='1'and clk'event then case state is when 0=> if (y='1' and x='1') or (y='1' and x='0') or (y='0' and x='0') then state<=0; z<='0'; else state<=1; z<='0'; end if;

when 3=> if (y='1' and x='1') then state<=0; z<='1'; elsif (y='1' and x='0') or (y='0' and x='0') then state<=0; z<='0'; else state<=1; z<='1'; end if; when others=>null; end case; end if; end process; end behavioral;

Port mapping-counter and detector

architecture behavioral of link1 is signal p:std_logic; component detect is port(y,x,clk,reset:in std_logic; z:out std_logic); end component; component counter is port(clk,reset:in std_logic; y:out std_logic); end component;

Y1 M1 M2

Clock

begin a1:count port map (clk=>clk,reset=>reset,y=>p); a2:detect port map (clk=>clk,reset=>reset,y=>p,x=>x,z=>z); end behavioral;

In a bit stream, count the number of @ character [ASCII code is 40H] in blocks of 256 characters. Each character is represented by a 8 bit ASCII code. Write HDL code and simulate.